M30833FJGP#U5 Renesas Electronics America, M30833FJGP#U5 Datasheet - Page 138

• Manufacturer Part Number: M30833FJGP#U5
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
. v
J
Figure 11.3 CM0 Register
2
0
1
C
9
3 .
B
8 /
0
1
3
0
3
J
G
4
a
0 -
o r
n
3 .
1
u
, 1
3
p
1
System Clock Control Register 0
b7
2
(
NOTES:
M
0
0
3
b6
1. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable).
2. When the PM07 bit in the PM0 register is set to "0" (BCLK output), set the CM01 to CM00 bits to
3. fc
4. When setting the CM04 bit to "1" (X
5. When entering the low-power consumption mode or on-chip oscillator low-power consumption mode,
6. When the CM05 bit is set to "1", the MCD register is set to "08
7. Once the CM06 bit is set to "1", it cannot be set "0" by program.
8. After the CM04 bit is set to "1" with a stable sub clock oscillation, set the CM07 bit to "1" from "0".
6
2
"00
CM01 to CM00 bits to "00
bits) in microprocessor or memory expansion mode, and the CM01 to CM00 bits are set to "00
"L" signal is output from port P5
port P8
the CM05 bit stops the main clock. The CM05 bit cannot detect whether the main clock stops or not.
To stop the main clock, set the CM05 bit to "1" after the CM07 bit is set to "1" with a stable sub clock
oscillation or after the CM21 bit in the CM2 register is set to "1" (on-chip oscillator clock). When the
CM05 bit is set to "1", X
to X
oscillation mode, the MCD register is not divided by eight even if the CM05 bit terminates X
After the CM05 bit is set to "0" with a stable main clock oscillation, set the CM07 bit to "0" from "1".
Do not set the CM07 bit and CM04 or CM05 bits simultaneously.
C
b5
32
Page 113
8 /
2
OUT
". When the PM15 to PM14 bits in the PM1 register is set to "01
b4
does not stop. When the CM02 bit is set to "1", the PLL clock cannot be used in wait mode.
, 3
7
b3
1
("H" level) via the feedback resistor.
M
and P8
3
b2
2
C
f o
b1
6
8 /
input mode) and the PU25 bit in the PUR2 register to "0" (no pull-up).
4
b0
3
8
) T
8
Symbol
CM00
CM01
CM02
CM04
CM05
CM06
CM07
OUT
(b3)
Bit
2
". When the PM07 bit is set to "1" (function selected in the CM01 to CM00
Symbol
CM0
becomes "H". The built-in feedback resistor remains on. X
3
Clock Output Function
Select Bit
In Wait Mode,
Peripheral
Function Clock Stop Bit
Reserved Bit
Port X
Main Clock (X
Stop Bit
Watchdog Timer
Function Select Bit
System Clock Select Bit
(port P5
CIN
-X
C
Bit Name
(5)
Switch Bit
COUT
3
(2)
does not function as an I/O port).
(1)
Address
0006
oscillation), set the PD8_7 to PD8_6 bits to "00
IN
-X
16
OUT
)
(8)
0 0 : I/O port P5
0 1 : Outputs f
1 0 : Outputs f
1 1 : Outputs f
b1 b0
0 : Peripheral clock does not stop in
1 : Peripheral clock stops in wait
Set to "1"
0 : Main clock oscillates
1 : Main clock stops
0: Clock selected by the CM21 bit
1: Sub clock
0 : I/O port function
1 : X
0 : Watchdog timer interrupt
1 : Reset
divided by MCD register setting
16
mode
wait mode
" (divide-by-8 mode). In on-chip
CIN
-X
(3)
2
(7)
" (ALE output to P5
COUT
After Reset
0000 X000
Function
C
8
32
3
oscillation function
(6)
2
IN
3
), set the
is pulled up
IN
11. Watchdog Timer
-X
2
(4)
2
" (with
OUT
", an
RW
RW
RW
RW
RW
RW
RW
RW
RW
.