M30833FJGP#U5 Renesas Electronics America, M30833FJGP#U5 Datasheet - Page 322

• Manufacturer Part Number: M30833FJGP#U5
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
. v
J
NOTES:
2
Table 21.17 Registers to be Used and Settings
Table 21.18 Pin Settings (1)
Table 21.19 Pin Settings (2)
0
GiBCR0
GiBCR1
GiPOCR0
GiPOCR1
GiPOCR3
GiPO0
GiPO3
GiFS
GiFE
GiERC
GiMR
GiCR
GiTB
GiRB
i = 0 to 1
NOTES:
Name
P7
P7
P7
P7
P7
Name
P8
1
C
9
Port
Port
1. Set the MOD2 to MOD0 bits in the corresponding register to "111
3 .
B
Register
1. The CKDIR bit in the GiMR register is set to "0" (internal clock)
8 /
3
4
5
6
7
0
0
1
function used).
3
0
3
J
G
4
a
0 -
n
o r
ISTxD1 output
ISCLK1 input
ISCLK1 output PS1_4 = 1
ISRxD1 input
ISTxD0 output
ISCLK0 input
ISCLK0 output PS1_7 = 1
ISRxD0 input
3 .
1
u
, 1
3
Function
Function
p
1
2
(
M
0
0
3
BCK1 to BCK0
DIV4 to DIV0
IT
7 to 0
7 to 0
7 to 0
7 to 0
15 to 0
15 to 0
FSC3,1,0
IFE3,1,0
7 to 0
GMD1 to GMD0
CKDIR
STPS
UFORM
IRS
TI
TXEPT
RI
TE
RE
IPOL
OPOL
7 to 0
15 to 0
6
2
C
8 /
Page 297
Bit
, 3
PS1 Register PSL1 Register PSC Register PD7 Register IPS Register
PS1_3 = 1
PS1_4 = 0
PS1_5 = 0
PS1_6 = 1
PS1_7 = 0
PS2 Register PD8 Register
PS2_0 = 0
M
3
2
C
f o
8 /
4
3
8
Set to "11
Select divide ratio of count source
Set to "0"
Set to "0001 0010
Set to "0000 0111
Set to "0000 0111
Set to "0000 0010
Set the bit rate
Set to a value smaller than the GiPO0 register
Set to "0"
Set to "1"
Set to "0010 0000
Set to "01
Select the internal clock or external clock
Set to "0"
Select either LSB first or MSB first
Select how the transmit interrupt is generated
Transmit buffer empty flag
Transmit register empty flag
Receive complete flag
Set to "1" to enable transmission and reception
Set to "1" to enable reception
Select ISRxD input polarity (usually set to "0")
Select ISTxD output polarity (usually set to "0")
Write data to be transmitted
Received data and error flag are stored
) T
2x(setting value + 2)
8
PSL1_3 = 0
-
PSL1_4 = 0
-
PSL1_6 = 0
-
-
Bit and Setting
PD8_0 = 0
f
2
2
BTi
"
"
2
2
2
2
2
"
"
"
"
"
(1)
Bit and Setting
PSC_3 = 1
-
PSC_4 = 1
-
PSC_6 = 0
-
-
IPS register
IPS0 = 0
21. Intelligent I/O (Group 0, 1 Communication Function)
= transfer clock frequency
-
PD7_4 = 0
-
PD7_5 = 0
-
PD7_7 = 0
-
-
Function
Register
2
" (output of the communication
(1)
(1)
-
IPS1 = 0
-
IPS1 = 0
-
IPS0 = 0
-
G1POCR0
-
G1POCR1
-
G0POCR0
-
G0POCR1
Register
(1)