M30833FJGP#U5 Renesas Electronics America, M30833FJGP#U5 Datasheet - Page 321

• Manufacturer Part Number: M30833FJGP#U5
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Table 21.16 Clock Synchronous Serial I/O Mode Specifications (Groups 0 and 1)
9 0
21.4.1 Clock Synchronous Serial I/O Mode (Groups 0 and 1)
Transfer Data Format
Transfer Clock
Transmit Start Condition
Receive Start Condition
Interrupt Request
Error Detection
Selectable Function
When the OPOL bit in the GiCR register is set to "0" (no ISTxDi output polarity inversed), the ISTxDi pin
outputs an "H" signal after selecting operation mode until transfer starts. When the OPOL bit is set to "1",
the ISTxDi pin outputs an "L" signal.
. 1
C
1. The transfer clock must be f
2. In clock synchronous serial I/O mode, set the RSHTE bit in the GiERC register (i=0, 1) to "1" (receive
3. When an overrun error occurs, the GiRB register is indeterminate.
B
In clock synchronous serial I/O mode, data is transmitted and received with the transfer clock. When the
internal clock is selected as the transfer clock, the channel 0 and channel 3 waveform generation func-
tions generate the internal clock. ISTxDi (i=0, 1), ISCLKi, and ISRxDi share pins with INPCi
and OUTCi
Table 21.16 lists specifications of clock synchronous serial I/O mode. Table 21.17 lists registers to be
used and their settings. Tables 21.18 to 21.21 list pin settings. Figure 21.39 shows an example of a
transmit and receive operation.
1 3
8 /
0
shift operation enabled).
3
3 0
J
G
- 4
n a
o r
1 0
3 .
u
, 1
1 3
p
Item
0 2
(
0
M
(1, 2)
6 0
to OUTCi
3
2
C
8 /
Page 296
, 3
M
2
.
3
2
Transfer data :
When the CKDIR bit in the GiMR register (i=0, 1) is set to "0" (internal clock) :
• The GiPO0 register determines the bit rate and the transfer clock is generated in
When the CKDIR bit is set to "1" (external clock) : input from the ISCLKi pin
Set registers associated with the waveform generation function, the GiMR register and the
GiERC register. Then set as written below after at least one transfer clock cycle:
• Set the TE bit in the GiCR register to "1" (transmit enable)
• Set the TI bit in the GiCR register to "0" (data in the GiTB register)
Set registers associated with the waveform generation function, the GiMR register and
GiERC register. Then set as written below after at least one transfer clock cycle:
• Set the RE bit in the GiCR register to "1" (receive enable)
• Set the TE bit to "1" (transmit enable)
• Set the TI bit to "0" (data in the GiTB register)
• While transmitting, one of the following conditions can be selected to set the SIOiTR
• While receiving, the following condition can be selected to set the SIOiRR bit to "1"
Data is transferred from the receive register to the GiRB register
Overrun error
This error occurs when the 8th bit of the next data is received before reading the GiRB register
• LSB first/MSB first
• ISTxDi and ISRxDi I/O polarity inverse
C
bit to "1" (see Figure 10.14):
(see Figure 10.14):
f o
Select either bit 0 or bit 7 to transmit/receive data
ISTxDi pin output level and ISRxDi pin input level are inversed
n : setting value of the GiPO0 register, 0000
phase-delayed waveform output mode by the channel 3 waveform generation func-
tion.
_
_
8 /
4
The IRS bit in the GiMR register is set to "0" (no data in the GiTB register) and data
is transferred to the transmit register from the GiTB register
transmit register is completed
The IRS bit is set to "1" (transmission completed) and data transfer from the
3
BTi
8 8
) T
divided by six or more.
(3)
8 bits long
21. Intelligent I/O (Group 0, 1 Communication Function)
Specification
16
to FFFF
16
0
to INPCi
2(n+2)
f
BTi
2