ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 107

• Manufacturer Part Number: ATA6603P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6603P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.11.1
4921E–AUTO–09/09
External Interrupt Control Register A – EICRA
The External Interrupt Control Register A contains control bits for interrupt sense control.
Table 4-41.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
Table 4-42.
• Bit 7..4 – Res: Reserved Bits
• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
Initial Value
Read/Write
ISC11
ISC01
These bits are unused bits in the ATA6602/ATA6603, and will always read as zero.
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the cor-
responding interrupt mask are set. The level and edges on the external INT1 pin that
activate the interrupt are defined in
detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock
period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
If low level interrupt is selected, the low level must be held until the completion of the cur-
rently executing instruction to generate an interrupt.
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the cor-
responding interrupt mask are set. The level and edges on the external INT0 pin that
activate the interrupt are defined in
detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock
period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
If low level interrupt is selected, the low level must be held until the completion of the cur-
rently executing instruction to generate an interrupt.
0
0
1
1
0
0
1
1
Bit
Interrupt 1 Sense Control
Interrupt 0 Sense Control
ISC10
ISC00
R
7
–
0
0
1
0
1
0
1
0
1
Description
The low level of INT1 generates an interrupt request.
Any logical change on INT1 generates an interrupt request.
The falling edge of INT1 generates an interrupt request.
The rising edge of INT1 generates an interrupt request.
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
R
6
–
0
R
5
–
0
Table
Table
R
4
–
0
4-41. The value on the INT1 pin is sampled before
4-42. The value on the INT0 pin is sampled before
ISC11
R/W
3
0
ATA6602/ATA6603
ISC10
R/W
2
0
ISC01
R/W
1
0
ISC00
R/W
0
0
EICRA
107