ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 39

MCU W/LIN TXRX REG WTCHDG 48-QFN

ATA6603P-PLQW

Manufacturer Part Number
ATA6603P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet

Specifications of ATA6603P-PLQW

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
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ATA6603P-PLQW
Manufacturer:
ATMEL
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ATA6603P-PLQW
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4.5
4.5.1
4921E–AUTO–09/09
AVR ATA6602/ATA6603 Memories
In-System Reprogrammable Flash Program Memory
This section describes the different memories in the ATA6602/ATA6603. The AVR architecture
has two main memory spaces, the Data Memory and the Program Memory space. In addition,
the ATA6602/ATA6603 features an EEPROM Memory for data storage. All three memory
spaces are linear and regular.
The ATA6602/ATA6603 contains 8/16 Kbytes On-chip In-System Reprogrammable Flash mem-
ory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized
as 2/4/8K x 16. For software security, the Flash Program memory space is divided into two sec-
tions, Boot Loader Section and Application Program Section in ATA6602 and ATA6603. See
SELFPRGEN description in section
SPMCSR” on page 287
The Flash memory has an endurance of at least 75,000 write/erase cycles. The
ATA6602/ATA6603 Program Counter (PC) is 11/12/13 bits wide, thus addressing the 2/4/8K
program memory locations. The operation of Boot Program section and associated Boot Lock
bits for software protection are described in detail in
Self-Programming, ATA6602 and ATA6603” on page
contains a detailed description on Flash Programming in SPI- or Parallel Programming mode.
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory instruction description).
Timing diagrams for instruction fetch and execution are presented in
ing” on page
Figure 4-7.
36.
Program Memory Map, ATA6602/ATA6603
for more details.
Application Flash Section
Program Memory
“Store Program Memory Control and Status Register –
“Boot Loader Support – Read-While-Write
282.
“Memory Programming” on page 298
ATA6602/ATA6603
0x0000
0x7FF
“Instruction Execution Tim-
39

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