ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 110

• Manufacturer Part Number: ATA6603P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6603P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.11.6
4.11.7
4.11.8
110
ATA6602/ATA6603
Pin Change Mask Register 2 – PCMSK2
Pin Change Mask Register 1 – PCMSK1
Pin Change Mask Register 0 – PCMSK0
Read/Write
Initial Value
• Bit 0 - PCIF0: Pin Change Interrupt Flag 0
• Bit 7..0 – PCINT23..16: Pin Change Enable Mask 23..16
• Bit 7 – Res: Reserved Bit
• Bit 6..0 – PCINT14..8: Pin Change Enable Mask 14..8
• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0
Read/Write
Initial Value
Initial Value
Read/Write
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes
set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to
the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is exe-
cuted. Alternatively, the flag can be cleared by writing a logical one to it.
Each PCINT23..16-bit selects whether pin change interrupt is enabled on the corresponding
I/O pin. If PCINT23..16 is set and the PCIE2 bit in PCICR is set, pin change interrupt is
enabled on the corresponding I/O pin. If PCINT23..16 is cleared, pin change interrupt on the
corresponding I/O pin is disabled.
This bit is an unused bit in the ATA6602/ATA6603, and will always read as zero.
Each PCINT14..8-bit selects whether pin change interrupt is enabled on the corresponding
I/O pin. If PCINT14..8 is set and the PCIE1 bit in PCICR is set, pin change interrupt is
enabled on the corresponding I/O pin. If PCINT14..8 is cleared, pin change interrupt on the
corresponding I/O pin is disabled.
Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding
I/O pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled
on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corre-
sponding I/O pin is disabled.
Bit
Bit
Bit
PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17
R/W
PCINT7
7
0
R/W
R
7
–
0
7
0
PCINT14 PCINT13 PCINT12 PCINT11 PCINT10
R/W
PCINT6
6
0
R/W
R/W
6
0
6
0
PCINT5
R/W
5
0
R/W
R/W
5
0
5
0
PCINT4
R/W
R/W
4
0
R/W
4
0
4
0
PCINT3
R/W
R/W
3
0
R/W
3
0
3
0
PCINT2
R/W
R/W
R/W
2
0
2
0
2
0
PCINT1
PCINT9
R/W
R/W
R/W
1
0
1
0
1
0
PCINT16
PCINT0
PCINT8
R/W
R/W
R/W
0
0
4921E–AUTO–09/09
0
0
0
0
PCMSK2
PCMSK1
PCMSK0