ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 68

MCU W/LIN TXRX REG WTCHDG 48-QFN

ATA6603P-PLQW

Manufacturer Part Number
ATA6603P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet

Specifications of ATA6603P-PLQW

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATA6603P-PLQW
Manufacturer:
ATMEL
Quantity:
2 000
Part Number:
ATA6603P-PLQW
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
4.8.3
Table 4-20.
68
Note:
V
Symbol
V
V
PORMAX
V
PORMIN
V
CCRR
POT
RST
1. Before rising, the supply has to be between
ATA6602/ATA6603
Power-on Reset
Power-on Reset Characteristics
Parameter
Power-on Reset Threshold Voltage (rising)
Power-on Reset Threshold Voltage (falling)
VCC Max. start voltage to ensure internal Power-on Reset signal
VCC Min. start voltage to ensure internal Power-on Reset signal
VCC Rise Rate to ensure Power-on Reset
RESET Pin Threshold Voltage
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in
POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply
voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after V
when V
Figure 4-16. MCU Start-up, RESET Tied to V
Figure 4-17. MCU Start-up, RESET Extended Externally
INTERNAL
INTERNAL
TIME-OUT
V
TIME-OUT
CC
RESET
RESET
RESET
CC
RESET
V
CC
decreases below the detection level.
V
CCRR
Table
4-20. The POR is activated whenever V
V
V
V
RST
PORMA X
PORMIN
V
PORMIN
(1)
CC
t
TOUT
and V
rise. The RESET signal is activated again, without any delay,
PORMAX
to ensure a Reset.
V
CC
RST
t
TOUT
Condition
0.1 V
0.01
-0.1
CC
CC
is below the detection level. The
Min
Typ
1.0
0.9
4921E–AUTO–09/09
0.9 V
Max
1.4
1.3
0.4
CC
Units
V/ms
V
V
V
V
V

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