ATTINY24-15MZ Atmel, ATTINY24-15MZ Datasheet - Page 130

• Manufacturer Part Number: ATTINY24-15MZ
• Description: MCU AVR 2K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 128Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: QFN EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.5.4
130
Atmel ATtiny24/44/84 [Preliminary]
USICR – USI Control Register
An interrupt will be generated when the flag is set while the USISIE bit in USICR and the
global interrupt enable flag are set. The flag will only be cleared by writing a logical one to the
USISIF bit. Clearing this bit will release the start detection hold of USCL in two-wire mode. A
start condition interrupt will wakeup the processor from all sleep modes.
• Bit 6 – USIOIF: Counter Overflow Interrupt Flag
This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). An
interrupt will be generated when the flag is set while the USIOIE bit in USICR and the global
interrupt enable flag are set. The flag is cleared if a logical one is written to the USIOIF bit or
by reading the USIBR register. Clearing this bit will release the counter overflow hold of SCL in
two-wire mode.
A counter overflow interrupt will wakeup the processor from Idle sleep mode.
• Bit 5 – USIPF: Stop Condition Flag
When two-wire mode is selected, the USIPF flag is set (one) when a stop condition is
detected. The flag is cleared by writing a logical one to this bit. Note that this is not an interrupt
flag. This signal is useful when implementing two-wire bus master arbitration.
• Bit 4 – USIDC: Data Output Collision
This bit is logical one when bit 7 in the Shift Register differs from the physical pin value. The
flag is only valid when Two-wire mode is used. This signal is useful when implementing
Two-wire bus master arbitration.
• Bits 3..0 – USICNT3..0: Counter Value
These bits reflect the current 4-bit counter value. The 4-bit counter value can be read or writ-
ten directly by the CPU.
The 4-bit counter increments by one for each clock generated either by the external clock
edge detector, by a timer/counter 0 compare match, or by software using USICLK or USITC
strobe bits. The clock source depends on the setting of the USICS1..0 bits. For external clock
operation, a special feature is added that allows the clock to be generated by writing to the
USITC strobe bit. This feature is enabled by writing a logical one to the USICLK bit while set-
ting an external clock source (USICS1 = 1).
Note that even when no wire mode is selected (USIWM1..0 = 0), the external clock input
(USCK/SCL) can still be used by the counter.
The Control Register includes interrupt enable control, wire mode setting, Clock Select setting,
and clock strobe.
Bit
0x0D (0x2D)
Read/Write
Initial Value
USISIE
R/W
7
0
USIOIE
R/W
6
0
USIWM1
R/W
5
0
USIWM0
R/W
4
0
USICS1
R/W
3
0
USICS0
R/W
2
0
USICLK
W
1
0
USITC
7701D–AVR–09/10
W
0
0
USICR