ATTINY24-15MZ Atmel, ATTINY24-15MZ Datasheet - Page 81

• Manufacturer Part Number: ATTINY24-15MZ
• Description: MCU AVR 2K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 128Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: QFN EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.8
7701D–AVR–09/10
Timer/Counter Timing Diagrams
• OCR0A changes its value from MAX, as in
• The timer starts counting from a value higher than the one in OCR0A, and for that reason
The timer/counter is a synchronous design, and the timer clock (clkT0) is, therefore, shown as
a clock enable signal in the following figures. The figures include information on when interrupt
flags are set.
tion.The figure shows the count sequence close to the max value in all modes other than
phase correct PWM mode.
Figure 13-8. Timer/Counter Timing Diagram, no Prescaling
Figure 13-9 on page 81
Figure 13-9. Timer/Counter Timing Diagram, with Prescaler (f
Figure 13-10 on page 82
except CTC mode and PWM mode, where OCR0A is TOP.
is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To
ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of
an up-counting Compare Match.
misses the compare match and, hence, the OCn change that would have happened on the
way up.
TCNTn
TCNTn
(clk
(clk
TOVn
TOVn
clk
clk
clk
clk
I/O
I/O
I/O
Tn
I/O
Tn
/1)
/8)
Figure 13-8 on page 81
MAX - 1
MAX - 1
shows the same timing data, but with the prescaler enabled.
shows the setting of OCF0B in all modes and OCF0A in all modes
Atmel ATtiny24/44/84 [Preliminary]
contains timing data for basic timer/counter opera-
MAX
MAX
Figure 13-7 on page
BOTTOM
BOTTOM
clk_I/O
80. When the OCR0A value
/8)
BOTTOM + 1
BOTTOM + 1
81