ATTINY24-15MZ Atmel, ATTINY24-15MZ Datasheet - Page 9

• Manufacturer Part Number: ATTINY24-15MZ
• Description: MCU AVR 2K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 128Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: QFN EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.4.1
7701D–AVR–09/10
SREG – AVR Status Register
The Status Register is not automatically stored when entering an interrupt routine and
restored when returning from an interrupt. This must be handled by software.
• Bit 7 – I: Global Interrupt Enable
The global interrupt enable bit must be set for the interrupts to be enabled. The individual inter-
rupt enable control is then performed in separate control registers. If the global interrupt
enable register is cleared, none of the interrupts are enabled independently of the individual
interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and
is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and
cleared by the application with the SEI and CLI instructions, as described in the instruction set
summary.
• Bit 6 – T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-
nation for the operated bit. A bit from a register in the register file can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the register file by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The half carry flag H indicates a half carry in some arithmetic operations. Half carry is useful in
BCD arithmetic. See the instruction set reference for detailed information.
• Bit 4 – S: Sign Bit, S = N
The S-bit is always an exclusive OR between the negative flag N and the two's complement
overflow flag V. See the "Instruction Set Description" for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The two's complement overflow flag V supports two's complement arithmetic. See the instruc-
tion set summary for detailed information.
• Bit 2 – N: Negative Flag
The negative flag N indicates a negative result in an arithmetic or logic operation. See the
instruction set summary for detailed information.
• Bit 1 – Z: Zero Flag
The zero flag Z indicates a zero result in an arithmetic or logic operation. See the instruction
set summary for detailed information.
• Bit 0 – C: Carry Flag
The carry flag C indicates a carry in an arithmetic or logic operation. See the instruction set
summary for detailed information.
Bit
0x3F (0x5F)
Read/Write
Initial Value
R/W
7
0
I
R/W
T
6
0
Atmel ATtiny24/44/84 [Preliminary]
V
R/W
H
5
0
R/W
S
4
0
R/W
3
V
0
R/W
N
2
0
R/W
1
Z
0
R/W
C
0
0
SREG
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