AT90CAN64-16AUR Atmel, AT90CAN64-16AUR Datasheet - Page 195

• Manufacturer Part Number: AT90CAN64-16AUR
• Description: MCU AVR 64K FLASH 16MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN64-16AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.11 USART Register Description
17.11.1
17.11.2
17.11.3
17.11.4
7679H–CAN–08/08
USART0 I/O Data Register – UDR0
USART1 I/O Data Register – UDR1
USART0 Control and Status Register A – UCSR0A
USART1 Control and Status Register A – UCSR1A
• Bit 7:0 – RxBn7:0: Receive Data Buffer (read access)
• Bit 7:0 – TxBn7:0: Transmit Data Buffer (write access)
The USARTn Transmit Data Buffer Register and USARTn Receive Data Buffer Registers share
the same I/O address referred to as USARTn Data Register or UDRn. The Transmit Data Buffer
Register (TXBn) will be the destination for data written to the UDRn Register location. Reading
the UDRn Register location will return the contents of the Receive Data Buffer Register (RXBn).
For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to
zero by the Receiver.
The transmit buffer can only be written when the UDREn flag in the UCSRnA Register is set.
Data written to UDRn when the UDREn flag is not set, will be ignored by the USARTn Transmit-
ter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter
will load the data into the Transmit Shift Register when the Shift Register is empty. Then the
data will be serially transmitted on the TxDn pin.
The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the
receive buffer is accessed.
• Bit 7 – RXCn: USARTn Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive
buffer will be flushed and consequently the RXCn bit will become zero. The RXCn flag can be
used to generate a Receive Complete interrupt (see description of the RXCIEn bit).
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Initial Value
Initial Value
Read/Write
Read/Write
Bit
Bit
RXC0
RXC1
R/W
R/W
7
0
7
0
R
R
7
0
7
0
TXC0
TXC1
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
UDRE0
UDRE1
R/W
R/W
5
0
5
0
R
R
5
1
5
1
R/W
R/W
FE0
FE1
4
0
4
0
4
R
0
4
R
0
RXB0[7:0]
RXB1[7:0]
TXB0[7:0]
TXB1[7:0]
R/W
R/W
DOR0
DOR1
3
0
3
0
R
R
3
0
3
0
R/W
R/W
UPE0
UPE1
2
0
2
0
R
R
2
0
2
0
AT90CAN32/64/128
R/W
R/W
U2X0
U2X1
1
0
1
0
R/W
R/W
1
0
1
0
R/W
R/W
MPCM0
MPCM1
0
0
0
0
R/W
R/W
0
0
0
0
UDR0 (Write)
UDR1 (Write)
UDR0 (Read)
UDR1 (Read)
UCSR0A
UCSR1A
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