AT90CAN64-16AUR Atmel, AT90CAN64-16AUR Datasheet - Page 207

• Manufacturer Part Number: AT90CAN64-16AUR
• Description: MCU AVR 64K FLASH 16MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN64-16AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.3.5
18.4
7679H–CAN–08/08
SDA
SCL
START
Multi-master Bus Systems, Arbitration and Synchronization
Combining Address and Data Packets Into a Transmission
Addr MSB
1
2
Acknowledge (ACK) is signalled by the receiver pulling the SDA line low during the ninth SCL
cycle. If the receiver leaves the SDA line high, a NACK is signalled. When the receiver has
received the last byte, or for some reason cannot receive any more bytes, it should inform the
transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first.
Figure 18-5. Data Packet Format
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets
and a STOP condition. An empty message, consisting of a START followed by a STOP condi-
tion, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement
handshaking between the master and the slave. The slave can extend the SCL low period by
pulling the SCL line low. This is useful if the clock speed set up by the master is too fast for the
slave, or the slave needs extra time for processing between the data transmissions. The slave
extending the SCL low period will not affect the SCL high period, which is determined by the
master. As a consequence, the slave can reduce the TWI data transfer speed by prolonging the
SCL duty cycle.
Figure 18-6
between the SLA+R/W and the STOP condition, depending on the software protocol imple-
mented by the application software.
Figure 18-6. Typical Data Transmission
The TWI protocol allows bus systems with several masters. Special concerns have been taken
in order to ensure that transmissions will proceed as normal, even if two or more masters initiate
a transmission at the same time. Two problems arise in multi-master systems:
SLA+R/W
Aggregate
Transmitter
SDA from
SDA from
SCL from
Receiver
Addr LSB
Master
SDA
7
shows a typical data transmission. Note that several data bytes can be transmitted
SLA+R/W
R/W
8
ACK
9
Data MSB
1
2
Data MSB
1
Data Byte
2
Data Byte
7
Data LSB
AT90CAN32/64/128
8
7
Data LSB
ACK
9
8
ACK
9
STOP, REPEATED
START or Next
Data Byte
STOP
207