AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 222

• Manufacturer Part Number: AT32UC3B0512-A2UT
• Description: IC MCU AVR32 512K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-A2UT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Controller Family/series: AT32UC3B
• No. Of I/o's: 44
• Ram Memory Size: 96KB
• Cpu Speed: 60MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.10 Master Mode
19.10.1
19.10.2
Figure 19-5. Master Mode Typical Application Block Diagram
19.10.3
19.10.4
19.10.5
32059K–03/2011
Definition
Application Block Diagram
Programming Master Mode
Master Mode Clock Timing
Master Transmitter Mode
Rp: Pull up value as given by the I²C Standard
Host with
Interface
TWI
The Master is the device which starts a transfer, generates a clock and stops it.
The following registers have to be programmed before entering Master mode:
The TWI module monitors the state of the TWCK line as required by the I²C specification. The
counter that determines the TWCK T
is detected by the module on TWCK, not when the module begins releasing or driving the TWCK
line. Thus, the CWGR.CHDIV and CLDIV fields do not alone determine the overall TWCK
period; they merely determine the T
(T
tion and synchronization delay of TWCK from the pin back into the TWI module. The TWI
module does not attempt to compensate for these delays, so the overall TWI clock period is
given by T
After the master initiates a Start condition when writing into the Transmit Holding Register, THR,
it sends a 7-bit slave address, configured in the Master Mode register (DADR in MMR), to notify
the slave device. The bit following the slave address indicates the transfer direction, 0 in this
case (MREAD = 0 in MMR).
TWD
TWCK
1. DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used
2. CKDIV + CHDIV + CLDIV: Determines clock waveform T
3. SVDIS: Disable the slave mode.
4. MSEN: Enable the master mode.
rise
Serial EEPROM
and T
to access slave devices in read or write mode.
Atmel TWI
Slave 1
high
fall
) are determined by the external circuitry on the TWCK pin as well as the propaga-
+T
fall
+T
low
+T
I²C RTC
Slave 2
rise
.
high
high
Controller
I²C LCD
Slave 3
or T
and T
low
low
duration is started whenever a high or low level
components, whereas the rise and fall times
I²C Temp.
Slave 4
Sensor
Rp
high
and T
Rp
low
.
AT32UC3B
VDD
222