AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 386
AT32UC3B0512-A2UT
Manufacturer Part Number
AT32UC3B0512-A2UT
Description
IC MCU AVR32 512K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B0512-A2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
AT32UC3B
No. Of I/o's
44
Ram Memory Size
96KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
MURATA
Quantity:
11 450
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
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22.7.2.13
32059K–03/2011
Management of OUT endpoints
•Overview
Figure 22-19. Abort Algorithm
OUT packets are sent by the host. All the data can be read which acknowledges or not the bank
when it is empty.
The endpoint must be configured first.
The RXOUTI bit is set at the same time as FIFOCON when the current bank is full. This triggers
an EPnINT interrupt if the Received OUT Data Interrupt Enable (RXOUTE) bit in UECONn is
one.
RXOUTI shall be cleared by software (by writing a one to the Received OUT Data Interrupt Clear
(RXOUTIC) bit) to acknowledge the interrupt, what has no effect on the endpoint FIFO.
The user then reads from the FIFO (see
DATA)” on page
composed of multiple banks, this also switches to the next bank. The RXOUTI and FIFOCON
bits are updated in accordance with the status of the next bank.
RXOUTI shall always be cleared before clearing FIFOCON.
The RWALL bit is set when the current bank is not empty, i.e. the software can read further data
from the FIFO.
TXINEC = 1
EPRSTn = 1
Abort Done
NBUSYBK
Endpoint
Abort
481) and clears the FIFOCON bit to free the bank. If the OUT endpoint is
== 0?
Yes
No
Yes
KILLBKS = 1
KILLBK
No
”USB Pipe/Endpoint n FIFO Data Register (USBFIFOn-
== 1?
Disable the TXINI interrupt.
Abort is based on the fact
that no bank is busy, i.e.,
that nothing has to be sent
Wait for the end of the
procedure
Kill the last written bank.
AT32UC3B
386
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