AT91SAM7X128B-AU Atmel, AT91SAM7X128B-AU Datasheet - Page 236

• Manufacturer Part Number: AT91SAM7X128B-AU
• Description: IC MCU 128KB FLASH 100LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X128B-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: JTAG, SPI, UART
• Maximum Clock Frequency: 55 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7X-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AT91SAM7xxxxx
• No. Of I/o's: 62
• Ram Memory Size: 32KB
• Cpu Speed: 55MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Cpu Family: 91S
• Device Core: ARM7TDMI
• Device Core Size: 32b
• Frequency (max): 55MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 62
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 27-5. Input Glitch Filter Timing
27.4.10
Figure 27-6. Input Change Interrupt Timings
236
if PIO_IFSR = 0
if PIO_IFSR = 1
Read PIO_ISR
PIO_PDSR
PIO_PDSR
Pin Level
Pin Level
PIO_ISR
SAM7X512/256/128 Preliminary
MCK
Input Change Interrupt
MCK
The PIO Controller can be programmed to generate an interrupt when it detects an input change
on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt Enable
Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and disable the
input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask
Register). As Input change detection is possible only by comparing two successive samplings of
the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is
available, regardless of the configuration of the I/O line, i.e. configured as an input only, con-
trolled by the PIO Controller or assigned to a peripheral function.
When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt
Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt
line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to gen-
erate a single interrupt signal to the Advanced Interrupt Controller.
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that
all the interrupts that are pending when PIO_ISR is read must be handled.
1 cycle
1 cycle
APB Access
up to 1.5 cycles
1 cycle
up to 2.5 cycles
2 cycles
APB Access
6120I–ATARM–06-Apr-11
up to 2 cycles
1 cycle
1 cycle