AT91SAM7X128B-AU Atmel, AT91SAM7X128B-AU Datasheet - Page 670

• Manufacturer Part Number: AT91SAM7X128B-AU
• Description: IC MCU 128KB FLASH 100LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X128B-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: JTAG, SPI, UART
• Maximum Clock Frequency: 55 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7X-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AT91SAM7xxxxx
• No. Of I/o's: 62
• Ram Memory Size: 32KB
• Cpu Speed: 55MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Cpu Family: 91S
• Device Core: ARM7TDMI
• Device Core Size: 32b
• Frequency (max): 55MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 62
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

674
Version
6120H
SAM7X512/256/128 Preliminary
Comments
Overview:
Table 3-1, “Signal Description List”
Section 6.1 ”JTAG Port Pins”, Section 6.2 ”Test Pin”
Section 8.4.3 ”Internal Flash”,
Remap Command.”
Figure 9-1,”System Controller Block Diagram”,
”Features”,
ADC:
Section 35.6.2 ”ADC Mode
“SHTIM: Sample & Hold Time” on page 495
Figure 35-1,”Analog-to-Digital Converter Block
Figure 35.5.5,”Conversion
AIC:
Section 23.8.16 ”AIC Spurious Interrupt Vector
Section 23.7.5 ”Protect
CAN:
Section 36.6.4.6 ”Error Interrupt
Section 36.8.5 ”CAN Status
ERRA, ERP.
DBGU:
Section 26.1
FFPI:
Section 20.2 ”Parallel Fast Flash
and Crystal Oscillator
Section 20.3 ”Serial Fast Flash
Crystal Oscillator
PMC:
”PMC System Clock Enable
Register”, bit field 11 contains PCK3.
PWM:
Section 33.6.12 ”PWM Channel Counter
RSTC:
Section 13.2.4.4 ”Software
SSC:
Section 31.8.3 ”SSC Receive Clock Mode
UDP:
Section 34.6 ”USB Device Port (UDP) User
Table 34-1, “USB Endpoint
Section 34.5.2.5 ”Transmit Data
Section 34.6.9 ”UDP Reset Endpoint
”Debug Unit
”Overview”, ...” two-pin UART can be used standalone for general purpose serial communication.” 5846
Mode”, writing PROT in AIC_DCR enables protection mode (3rd paragraph).
(DBGU)”, added
Triggers”, update to the third paragraph detailing hardware trigger.
Reset”, PERRST must be used with PROCRST, except for debug purposes.
Register”, PRESCAL and STARTUP bit fields widened.
Description”, footnote added to Dual-Bank heading.
Register”, added references to the new chapter in bit descriptions, WARN, BOFF,
Register”,
updated: “At any time, the Flash is mapped ... if GPNVM bit 2 is set and before the
Programming”,
Handler”, added to datasheet.
Cancellation”, added to datasheet
Programming”,
footnote added to JTAGSEL, ERASE and TST pin comments.
Register”, added steps to clear endpoints.
”PMC System Clock Disable Register”
Register”, typos corrected in bit description.
”Mode for General Purpose 2-wire UART Serial Communication”
Register”, corrected bit name to STTDLY.
Interface”, reset value for UDP_RST_EP is 0x000_0000.
formula updated in bit description.
Section 20.3.1 ”Device
RTT is reset by power_on_reset.
Diagram”, VDDANA replaced by VDDIN. PMC added to figure.
Register”, typo fixed in bit fields. (SIQV is SIVR).
Section 20.2.1 ”Device
and
Section 6.4 ”ERASE Pin”,
Configuration”, added status of PIOs and
Configuration”, added status of PIOs
and
”PMC System Clock Status
updated.
6120I–ATARM–06-Apr-11
Change
Request
Ref.
5064
5850
5223
5846
4430
5254
rfo
4749
5193
4736
5989
5722
5185
5049
5150