AT91SAM7X128B-AU Atmel, AT91SAM7X128B-AU Datasheet - Page 636

IC MCU 128KB FLASH 100LQFP

AT91SAM7X128B-AU

Manufacturer Part Number
AT91SAM7X128B-AU
Description
IC MCU 128KB FLASH 100LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets

Specifications of AT91SAM7X128B-AU

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
JTAG, SPI, UART
Maximum Clock Frequency
55 MHz
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7X-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AT91SAM7xxxxx
No. Of I/o's
62
Ram Memory Size
32KB
Cpu Speed
55MHz
No. Of Timers
1
Rohs Compliant
Yes
Cpu Family
91S
Device Core
ARM7TDMI
Device Core Size
32b
Frequency (max)
55MHz
Total Internal Ram Size
32KB
# I/os (max)
62
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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41.2
636
Errata Summary by Product and Revision or Manufacturing Number
SAM7X512/256/128 Preliminary
Table 41-1.
Part
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
CAN
CAN
EFC1
EFC2
EMAC
EMAC
EMAC
PIO
PIO
PIO
PWM
PWM
PWM
PWM
RTT
SPI
SPI
Errata
DRDY Bit Cleared
DRDY not Cleared on Disable
DRDY Possibly Skipped due to CDR Read
Possible Skip on DRDY when Disabling a Channel
GOVRE Bit is not Updated
GOVRE Bit is not Set when Reading CDR
GOVRE Bit is not Set when Disabling a Channel
OVRE Flag Behavior
EOC Set although Channel Disabled
Spurious Clear of EOC Flag
Sleep Mode
Low Power Mode and Error Frame
Low Power Mode and Pending Transmit Messages
Embedded Flash Access Time 1
Embedded Flash Access Time 2
RMII Mode
Possible Event Loss when Reading EMAC_ISR
Possible Event Loss when Reading the Statistics Register Block
Leakage on PB27 - PB30
Electrical Characteristics on NRST and PA0-PA30 and PB0 -
PB26
Drive Low NRST, PA0-PA30 and PB0-PB26
Update when PWM_CCNTx = 0 or 1
Update when PWM_CPRDx = 0
Counter Start Value
Behavior of CHIDx Status Bits in the PWM_SR Register
Possible Event Loss when Reading RTT_SR
Software Reset Must be Written Twice
Bad Behavior when CSAAT = 1 and SCBR = 1
Errata Summary Table
Revision or Manufacturing Number
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6120I–ATARM–06-Apr-11
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