P89LPC9381FDH,512 NXP Semiconductors, P89LPC9381FDH,512 Datasheet - Page 25
![IC 80C51 MCU FLASH 4K 28-TSSOP](/photos/6/52/65262/568-28-tssop_sot361-1_sml.jpg)
P89LPC9381FDH,512
Manufacturer Part Number
P89LPC9381FDH,512
Description
IC 80C51 MCU FLASH 4K 28-TSSOP
Manufacturer
NXP Semiconductors
Series
LPC900r
Datasheet
1.P89LPC9381FA112.pdf
(60 pages)
Specifications of P89LPC9381FDH,512
Core Processor
8051
Core Size
8-Bit
Speed
18MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-TSSOP
Processor Series
P89LPC9x
Core
80C51
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
18 MHz
Number Of Programmable I/os
26
Number Of Timers
2
Operating Supply Voltage
2.4 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
622-1014 - BOARD FOR LPC9XX TSSOP622-1011 - BOARD FOR LPC938 TSSOP622-1008 - BOARD FOR LPC9103 10-HVSON622-1006 - SOCKET ADAPTER BOARDMCB900K - BOARD PROTOTYPE NXP 89LPC9EPM900K - EMULATOR/PROGRAMMER NXP P89LPC9568-1759 - EMULATOR DEBUGGER/PROGRMMR LPC9X568-1758 - BOARD EVAL FOR LPC93X MCU FAMILY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
935280615512
P89LPC9381FDH
P89LPC9381FDH
P89LPC9381FDH
P89LPC9381FDH
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
P89LPC9381FDH,512
Manufacturer:
LT
Quantity:
2 340
Philips Semiconductors
P89LPC9381_1
Product data sheet
7.16.1 Reset vector
7.16 Reset
7.17 Timers/counters 0 and 1
The P1[5]/RST pin can function as either an active-LOW reset input or as a digital input,
P1[5]. The RPE (Reset Pin Enable) bit in UCFG1, when set to ‘1’, enables the external
reset input function on P1[5]. When cleared, P1[5] may be used as an input pin.
Remark: During a power-up sequence, The RPE selection is overridden and this pin will
always functions as a reset input. An external circuit connected to this pin should not
hold this pin LOW during a power-on sequence as this will keep the device in reset.
After power-up this input will function either as an external reset input or as a digital input
as defined by the RPE bit. Only a power-up reset will temporarily override the selection
defined by RPE bit. Other sources of reset will not override the RPE bit.
Reset can be triggered from the following sources:
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read
this register to determine the most recent reset source. These flag bits can be cleared in
software by writing a ‘0’ to the corresponding bit. More than one flag bit may be set:
Following reset, the P89LPC9381 will fetch instructions from either address 0000H or the
Boot address. The Boot address is formed by using the Boot Vector as the high byte of the
address and the low byte of the address = 00H.
The Boot address will be used if a UART break reset occurs, or the non-volatile Boot
Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see
P89LPC9381 User’s Manual ). Otherwise, instructions will be fetched from address 0000H.
The P89LPC9381 has two general purpose counter/timers which are upward compatible
with the standard 80C51 Timer 0 and Timer 1. Both can be configured to operate either as
timers or event counter. An option to automatically toggle the T0 and/or T1 pins upon timer
overflow has been added.
In the ‘Timer’ function, the register is incremented every machine cycle.
In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T0 or T1. In this function, the external input is sampled
once during every machine cycle.
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•
•
•
•
•
•
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External reset pin (during power-up or if user configured via UCFG1);
Power-on detect;
Brownout detect;
Watchdog timer;
Software reset;
UART break character detect reset.
During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.
For any other reset, previously set flag bits that have not been cleared will remain set.
Rev. 01 — 8 September 2006
8-bit microcontroller with 10-bit ADC
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
P89LPC9381
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