P89LPC9381FDH,512 NXP Semiconductors, P89LPC9381FDH,512 Datasheet - Page 59
![IC 80C51 MCU FLASH 4K 28-TSSOP](/photos/6/52/65262/568-28-tssop_sot361-1_sml.jpg)
P89LPC9381FDH,512
Manufacturer Part Number
P89LPC9381FDH,512
Description
IC 80C51 MCU FLASH 4K 28-TSSOP
Manufacturer
NXP Semiconductors
Series
LPC900r
Datasheet
1.P89LPC9381FA112.pdf
(60 pages)
Specifications of P89LPC9381FDH,512
Core Processor
8051
Core Size
8-Bit
Speed
18MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-TSSOP
Processor Series
P89LPC9x
Core
80C51
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
18 MHz
Number Of Programmable I/os
26
Number Of Timers
2
Operating Supply Voltage
2.4 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
622-1014 - BOARD FOR LPC9XX TSSOP622-1011 - BOARD FOR LPC938 TSSOP622-1008 - BOARD FOR LPC9103 10-HVSON622-1006 - SOCKET ADAPTER BOARDMCB900K - BOARD PROTOTYPE NXP 89LPC9EPM900K - EMULATOR/PROGRAMMER NXP P89LPC9568-1759 - EMULATOR DEBUGGER/PROGRMMR LPC9X568-1758 - BOARD EVAL FOR LPC93X MCU FAMILY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
935280615512
P89LPC9381FDH
P89LPC9381FDH
P89LPC9381FDH
P89LPC9381FDH
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
P89LPC9381FDH,512
Manufacturer:
LT
Quantity:
2 340
Philips Semiconductors
18. Contents
1
2
2.1
2.2
3
3.1
4
5
6
6.1
6.2
7
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.12.1
7.13
7.13.1
7.13.1.1
7.13.1.2
7.13.1.3
7.13.1.4
7.13.2
7.13.3
7.14
7.14.1
7.14.2
7.15
7.15.1
7.15.2
7.15.3
7.16
P89LPC9381_1
Product data sheet
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5
Pinning information . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . 10
Principal features . . . . . . . . . . . . . . . . . . . . . . . 1
Additional features . . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Special function registers . . . . . . . . . . . . . . . . 10
Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . 17
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clock definitions . . . . . . . . . . . . . . . . . . . . . . . 17
CPU clock (OSCCLK). . . . . . . . . . . . . . . . . . . 17
Low speed oscillator option . . . . . . . . . . . . . . 17
Medium speed oscillator option . . . . . . . . . . . 17
High speed oscillator option . . . . . . . . . . . . . . 17
Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 17
On-chip RC oscillator option . . . . . . . . . . . . . . 18
Watchdog oscillator option . . . . . . . . . . . . . . . 18
External clock input option . . . . . . . . . . . . . . . 18
CCLK wake-up delay . . . . . . . . . . . . . . . . . . . 19
CCLK modification: DIVM register . . . . . . . . . 19
Low power select . . . . . . . . . . . . . . . . . . . . . . 19
Memory organization . . . . . . . . . . . . . . . . . . . 19
Data RAM arrangement . . . . . . . . . . . . . . . . . 20
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
External interrupt inputs . . . . . . . . . . . . . . . . . 20
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Port configurations . . . . . . . . . . . . . . . . . . . . . 22
Quasi-bidirectional output configuration . . . . . 22
Open-drain output configuration . . . . . . . . . . . 22
Input-only configuration . . . . . . . . . . . . . . . . . 23
Push-pull output configuration . . . . . . . . . . . . 23
Port 0 analog functions . . . . . . . . . . . . . . . . . . 23
Additional port features. . . . . . . . . . . . . . . . . . 23
Power monitoring functions. . . . . . . . . . . . . . . 23
Brownout detection . . . . . . . . . . . . . . . . . . . . . 23
Power-on detection . . . . . . . . . . . . . . . . . . . . . 24
Power reduction modes . . . . . . . . . . . . . . . . . 24
Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power-down mode . . . . . . . . . . . . . . . . . . . . . 24
Total Power-down mode . . . . . . . . . . . . . . . . . 24
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Rev. 01 — 8 September 2006
7.16.1
7.17
7.17.1
7.17.2
7.17.3
7.17.4
7.17.5
7.17.6
7.18
7.19
7.19.1
7.19.2
7.19.3
7.19.4
7.19.5
7.19.6
7.19.7
7.19.8
7.19.9
7.19.10
7.20
7.21
7.21.1
7.22
7.22.1
7.22.2
7.22.3
7.23
7.24
7.25
7.25.1
7.25.2
7.26
7.26.1
7.26.2
7.26.3
7.26.4
7.26.5
7.26.6
7.26.7
7.26.8
7.26.9
7.26.10
7.27
7.28
8
ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Timers/counters 0 and 1 . . . . . . . . . . . . . . . . 25
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Timer overflow toggle output . . . . . . . . . . . . . 26
RTC/system timer. . . . . . . . . . . . . . . . . . . . . . 26
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Baud rate generator and selection . . . . . . . . . 27
Framing error . . . . . . . . . . . . . . . . . . . . . . . . . 28
Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Double buffering . . . . . . . . . . . . . . . . . . . . . . . 28
Transmit interrupts with double buffering
enabled (modes 1, 2 and 3) . . . . . . . . . . . . . . 28
The 9
(modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . 28
I
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Typical SPI configurations . . . . . . . . . . . . . . . 32
Analog comparators . . . . . . . . . . . . . . . . . . . . 34
Internal reference voltage. . . . . . . . . . . . . . . . 34
Comparator interrupt . . . . . . . . . . . . . . . . . . . 34
Comparators and power reduction modes . . . 34
KBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 36
Additional features . . . . . . . . . . . . . . . . . . . . . 36
Software reset . . . . . . . . . . . . . . . . . . . . . . . . 36
Dual data pointers . . . . . . . . . . . . . . . . . . . . . 36
Flash program memory . . . . . . . . . . . . . . . . . 37
General description . . . . . . . . . . . . . . . . . . . . 37
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Flash organization . . . . . . . . . . . . . . . . . . . . . 37
Using flash as data storage . . . . . . . . . . . . . . 37
Flash programming and erasing. . . . . . . . . . . 37
ICP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
IAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Power-on reset code execution . . . . . . . . . . . 39
Hardware activation of the bootloader . . . . . . 39
User configuration bytes. . . . . . . . . . . . . . . . . 39
User sector security bytes . . . . . . . . . . . . . . . 39
2
C-bus serial interface. . . . . . . . . . . . . . . . . . 29
8-bit microcontroller with 10-bit ADC
th
bit (bit 8) in double buffering
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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