Z8F012ASB020SG Zilog, Z8F012ASB020SG Datasheet - Page 57

• Manufacturer Part Number: Z8F012ASB020SG
• Description: IC ENCORE XP MCU FLASH 1K 8SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F012ASB020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 16 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: Z8F012Ax
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8F04A08100KITG, Z8F04A28100KITG, ZENETSC0100ZACG, ZENETSC0100ZACG, ZUSBOPTSC01ZACG, ZUSBSC00100ZAC, ZUSBSC00100ZACG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4039; Z8F012ASB020SG

Table 17. Port A–D GPIO Address Registers (PxADDR)
BITS
FIELD
RESET
R/W
ADDR
PS022825-0908
PADDR[7:0]
09H–FFH
00H
01H
02H
03H
04H
05H
06H
07H
08H
Port A–D Address Registers
Port A–D Control Registers
R/W
7
The Port A–D Address registers select the GPIO Port functionality accessible through the
Port A–D Control registers. The Port A–D Address and Control registers combine to pro-
vide access to all GPIO Port controls
PADDR[7:0]—Port Address
The Port Address selects one of the sub-registers accessible through the Port Control reg-
ister.
The Port A–D Control registers set the GPIO port operation. The value in the correspond-
ing Port A–D Address register determines which sub-register is read from or written to by
a Port A–D Control register transaction
Port Control sub-register accessible using the Port A–D Control Registers
No function. Provides some protection against accidental Port reconfiguration.
Data Direction.
Alternate Function.
Output Control (Open-Drain).
High Drive Enable.
Stop Mode Recovery Source Enable.
Pull-up Enable.
Alternate Function Set 1.
Alternate Function Set 2.
No function.
R/W
6
R/W
5
FD0H, FD4H, FD8H, FDCH
R/W
4
PADDR[7:0]
(Table
(Table
00H
17).
R/W
18).
3
Z8 Encore! XP
R/W
2
General-Purpose Input/Output
Product Specification
R/W
1
®
F082A Series
R/W
0
46