F272-BAGE-T-TR STMicroelectronics, F272-BAGE-T-TR Datasheet - Page 147
F272-BAGE-T-TR
Manufacturer Part Number
F272-BAGE-T-TR
Description
MCU 16BIT 256K FLASH 144-TQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet
1.F272-BAGE-T-TR.pdf
(182 pages)
Specifications of F272-BAGE-T-TR
Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-TQFP, 144-VQFP
Data Bus Width
16 bit
Data Ram Size
20 KB
Interface Type
ASC, CAN, I2C, SSC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
111
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
F272-BAGE-T-TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
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ST10F272B/ST10F272E
24.8
24.8.1
24.8.2
AC characteristics
Test waveforms
Figure 43. Input / output waveforms
Figure 44. Float waveforms
Definition of internal timing
The internal operation of the ST10F272 is controlled by the internal CPU clock f
edges of the CPU clock can trigger internal (for example pipeline) or external (for example
bus cycles) operations.
The specification of the external timing (AC Characteristics) therefore depends on the time
between two consecutive edges of the CPU clock, called “TCL”.
The CPU clock signal can be generated by different mechanisms. The duration of TCL and
its variation (and also the derived external timing) depends on the mechanism used to
generate f
This influence must be regarded when calculating the timings for the ST10F272.
The example for PLL operation shown in
The mechanism used to generate the CPU clock is selected during reset by the logic levels
on pins P0.15-13 (P0H.7-5).
0.4V
2.4V
V
LOAD
For timing purposes a port pin is no longer floating when V
It begins to float when a 100mV change from the loaded V
CPU
AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’.
Timing measurements are made at V
V
V
.
LOAD
LOAD
+ 0.1V
- 0.1V
2.0V
0.8V
Test Points
Figure 45
Reference
Timing
Points
V
IH
V
OL
OH
min. for a logic ‘1’ and V
2.0V
0.8V
refers to a PLL factor of 4.
OH
LOAD
/V
Electrical characteristics
OL
changes of ±100mV.
level occurs (I
IL
max for a logic ‘0’.
V
V
OL
OH
+ 0.1V
- 0.1V
CPU
OH
/I
. Both
OL
147/182
= 20m
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