F272-BAGE-T-TR STMicroelectronics, F272-BAGE-T-TR Datasheet - Page 87

• Manufacturer Part Number: F272-BAGE-T-TR
• Description: MCU 16BIT 256K FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F272-BAGE-T-TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 20 KB
• Interface Type: ASC, CAN, I2C, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

ST10F272B/ST10F272E
20.3
Figure 20. Asynchronous hardware RESET (EA = 0)
Exit from asynchronous reset state
When the RSTIN pin is pulled high, the device restarts: as already mentioned, if internal
FLASH is used, the restarting occurs after the embedded FLASH initialization routine is
completed. The system configuration is latched from Port0: ALE, RD and WR/WRL pins are
driven to their inactive level. The ST10F272 starts program execution from memory location
00'0000h in code segment 0. This starting location will typically point to the general
initialization routine. Timing of asynchronous Hardware Reset sequence are summarized in
Figure 19
Synchronous reset (warm reset)
A synchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at high
level. In order to properly activate the internal reset logic of the device, the RSTIN pin must
be held low, at least, during 4 TCL (2 periods of CPU clock): refer also to
details on minimum reset pulse duration. The I/O pins are set to high impedance and
RSTOUT pin is driven low. After RSTIN level is detected, a short duration of a maximum of
12 TCL (six periods of CPU clock) elapses, during which pending internal hold states are
cancelled and the current internal access cycle if any is completed. External bus cycle is
aborted. The internal pull-down of RSTIN pin is activated if bit BDRSTEN of SYSCON
register was previously set by software. Note that this bit is always cleared on power-on or
after a reset sequence.
Note 1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed)
Note 2. 3 to 8 TCL depending on clock source selection.
Longer than 500ns to take into account of Input Filter on RSTIN pin
RPD
RSTIN
RSTF
(After Filter)
P0[15:13]
P0[12:2]
P0[1:0]
ALE
RST
and
Figure
20.
not transparent
not transparent
≤ 500 ns
≥ 50 ns
not transparent
transparent
transparent
1)
system start-up configuration
Latching point of Port0 for
≤ 500 ns
≥ 50 ns
3..4 TCL
3..8 TCL
2)
Section 20.1
not t.
not t.
not t.
8 TCL
System reset
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for