F272-BAGE-T-TR STMicroelectronics, F272-BAGE-T-TR Datasheet - Page 93

• Manufacturer Part Number: F272-BAGE-T-TR
• Description: MCU 16BIT 256K FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F272-BAGE-T-TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 20 KB
• Interface Type: ASC, CAN, I2C, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

ST10F272B/ST10F272E
20.4
Figure 24. Synchronous long hardware RESET (EA = 0)
Software reset
A software reset sequence can be triggered at any time by the protected SRST (software
reset) instruction. This instruction can be deliberately executed within a program, e.g. to
leave bootstrap loader mode, or on a hardware trap that reveals system failure.
On execution of the SRST instruction, the internal reset sequence is started. The
microcontroller behavior is the same as for a synchronous short reset, except that only bits
P0.12...P0.8 are latched at the end of the reset sequence, while previously latched, bits
P0.7...P0.2 are cleared (that is written at ‘1’).
A Software reset is always taken as synchronous: there is no influence on Software Reset
behavior with RPD status. In case Bidirectional Reset is selected, a Software Reset event
pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled
low even though Bidirectional Reset is selected.
3. 3 to 8 TCL depending on clock source selection.
RSTIN
RSTF
(After Filter)
P0[15:13]
P0[12:2]
P0[1:0]
Notes:
1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation),
2. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the
ALE
RST
RSTOUT
RPD
the asynchronous reset is then immediately entered.
internal filter (refer to Section 21.1).
≤ 500 ns
≥ 50 ns
4 TCL
200
2)
12 TCL
µ
A Discharge
not transparent
≤ 500 ns
≥ 50 ns
1024+8 TCL
1024+8 TCL
not transparent
transparent
At this time RSTF is sampled LOW
so it is LONG reset
transparent
≤ 500 ns
≥ 50 ns
3..4 TCL
1)
3..8 TCL
V
RPD
> 2.5V Asynchronous Reset not entered
3)
not t.
not t.
not t.
8 TCL
System reset
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