F272-BAGE-T-TR STMicroelectronics, F272-BAGE-T-TR Datasheet - Page 176

• Manufacturer Part Number: F272-BAGE-T-TR
• Description: MCU 16BIT 256K FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F272-BAGE-T-TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 20 KB
• Interface Type: ASC, CAN, I2C, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Electrical characteristics
Table 82.
1. Maximum Baudrate is in reality 8Mbaud, that can be reached with 64MHz CPU clock and <SSCBR> set to ‘3h’, or with
2. Formula for SSC Clock Cycle time: t
176/182
t
t
317
318
Symbol
48MHz CPU clock and <SSCBR> set to ‘2h’. When 40MHz CPU clock is used the maximum baudrate cannot be higher
than 6.6Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> may be used only
with CPU clock lower than 32MHz (after checking that resulting timings are suitable for the master).
Where <SSCBR> represents the content of the SSC Baudrate register, taken as unsigned 16-bit integer.
Minimum limit allowed for t
SR
SR
SSC slave mode timings (continued)
Figure 62. SSC slave timing
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock
2. The bit timing is repeated for all bits to be transmitted or received.
Read data setup time before latch
edge, phase error detection off
(SSCPEN = 0)
Read data hold time after latch
edge, phase error detection off
(SSCPEN = 0)
SCLK
MRST
MTSR
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
Parameter
1)
310
is 125ns (corresponding to 8Mbaud).
t
315
310
t
1st in bit
317
= 4 TCL * (<SSCBR> + 1)
1st out bit
t
310
t
318
t
t
314
315
t
311
(<SSCBR> = 0002h)
2nd out bit
min.
@F
31
2nd in bit
Max. Baudrate
6
t
312
6.6 MBd
CPU
= 40MHz
t
t
316
313
(1)
max.
)
–
–
2)
2TCL + 6
t
(<SSCBR> = 0001h -
315
min.
Variable Baudrate
Last in bit
t
6
317
ST10F272B/ST10F272E
Last out bit
FFFFh)
t
318
max.
–
–
Unit
ns
ns