S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 329
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S9S12HY64J0MLL
Manufacturer Part Number
S9S12HY64J0MLL
Description
MCU 64K FLASH AUTO 100-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12HA32J0CLL.pdf
(792 pages)
Specifications of S9S12HY64J0MLL
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LCD, Motor control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-LQFP
Controller Family/series
S12
No. Of I/o's
80
Ram Memory Size
4KB
Cpu Speed
64MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
S12HY
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
DEMO9S12HY64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12HY64J0MLL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
S9S12HY64J0MLL
Manufacturer:
FREESCALE
Quantity:
20 000
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1. Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1)
9.3.2.16
This register reflects the status of the MSCAN transmit error counter.
1. Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1)
Freescale Semiconductor
Module Base + 0x000E
Module Base + 0x000F
Write: Unimplemented
Write: Unimplemented
Reset:
Reset:
W
W
R
R
MSCAN Transmit Error Counter (CANTXERR)
RXERR7
TXERR7
Reading this register when in any other mode other than sleep or
initialization mode may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Writing to this register when in special modes can alter the MSCAN
functionality.
Reading this register when in any other mode other than sleep or
initialization mode, may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Writing to this register when in special modes can alter the MSCAN
functionality.
0
0
7
7
Figure 9-19. MSCAN Transmit Error Counter (CANTXERR)
Figure 9-18. MSCAN Receive Error Counter (CANRXERR)
RXERR6
TXERR6
= Unimplemented
= Unimplemented
6
0
6
0
MC9S12HY/HA-Family Reference Manual Rev. 1.04
RXERR5
TXERR5
0
0
5
5
RXERR4
TXERR4
NOTE
NOTE
4
0
4
0
Freescale’s Scalable Controller Area Network (S12MSCANV3)
RXERR3
TXERR3
0
0
3
3
RXERR2
TXERR2
2
0
2
0
Access: User read/write
Access: User read/write
RXERR1
TXERR1
0
0
1
1
RXERR0
TXERR0
0
0
0
0
329
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