S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 777
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
S9S12HY64J0MLL
Manufacturer Part Number
S9S12HY64J0MLL
Description
MCU 64K FLASH AUTO 100-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12HA32J0CLL.pdf
(792 pages)
Specifications of S9S12HY64J0MLL
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LCD, Motor control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-LQFP
Controller Family/series
S12
No. Of I/o's
80
Ram Memory Size
4KB
Cpu Speed
64MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
S12HY
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
DEMO9S12HY64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12HY64J0MLL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
S9S12HY64J0MLL
Manufacturer:
FREESCALE
Quantity:
20 000
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Detailed MSCAN Foreground Receive and Transmit Buffer Layout (continued)
Freescale Semiconductor
Address
0x015C–
Address
0x0150–
0x0154–
0x0158–
0x0160–
0x0170–
0xXXX0
0x014C
0x014D
0x0145
0x0146
0x0147
0x0148
0x0149
0x014A
0x014B
0x014E
0x014F
0x0153
0x0157
0x015B
0x015F
0x016F
0x017F
CANIDMR0–
CANIDMR4–
CANRXERR
CANIDAR0–
CANIDAR4–
CANxRIDR0 W
CANTXERR
Extended ID
Standard ID
CANTBSEL
CANIDMR3
CANIDMR7
CANIDAR3
CANIDAR7
CANRXFG
CANTXFG
CANTFLG
CANTARQ
CANTAAK
CANMISC
CANRIER
CANTIER
CANIDAC
Reserved
Name
Name
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R RXERR7
R TXERR7
R
R
R
R
R
R
WUPIE
Bit 7
Bit 7
AM7
AM7
ID28
ID10
AC7
AC7
0
0
0
0
0
0
0
0
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
(See
(See
RXERR6
TXERR6
CSCIE
Bit 6
Bit 6
AM6
AM6
ID27
AC6
AC6
ID9
0
0
0
0
0
0
0
0
Detailed MSCAN Foreground Receive and Transmit Buffer
Detailed MSCAN Foreground Receive and Transmit Buffer
RSTATE1
RXERR5
TXERR5
IDAM1
Bit 5
Bit 5
AM5
AM5
ID26
AC5
AC5
ID8
0
0
0
0
0
0
0
FOREGROUND TRANSMIT BUFFER
FOREGROUND RECEIVE BUFFER
RSTATE0
RXERR4
TXERR4
IDAM0
Bit 4
Bit 4
AM4
AM4
ID25
AC4
AC4
ID7
0
0
0
0
0
0
0
TSTATE1
RXERR3
TXERR3
Bit 3
Bit 3
ID24
AM3
AM3
AC3
AC3
ID6
0
0
0
0
0
0
0
0
TSTATE0
ABTRQ2
RXERR2
TXERR2
ABTAK2
TXEIE2
IDHIT2
TXE2
Bit 2
Bit 2
ID23
AM2
AM2
TX2
AC2
AC2
ID5
0
0
Detailed Register Address Map
RXERR1
ABTRQ1
TXERR1
ABTAK1
TXEIE1
IDHIT1
OVRIE
TXE1
Bit 1
Bit 1
ID22
AM1
AM1
TX1
AC1
AC1
Layout)
Layout)
ID4
0
0
BOHOLD
RXERR0
ABTRQ0
TXERR0
ABTAK0
TXEIE0
IDHIT0
RXFIE
TXE0
Bit 0
AM0
AM0
Bit 0
ID21
TX0
AC0
AC0
ID3
0
777
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