MCHC908GR8AMFAE Freescale Semiconductor, MCHC908GR8AMFAE Datasheet - Page 125

• Manufacturer Part Number: MCHC908GR8AMFAE
• Description: IC MCU 8K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8AMFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LQFP
• Processor Series: HC08G
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

T1CH1 and T1CH0 — Timer 1 Channel I/O Bits
SPSCK — SPI Serial Clock
MOSI — Master Out/Slave In
MISO — Master In/Slave Out
SS — Slave Select
12.5.2 Data Direction Register D
Data direction register D (DDRD) determines whether each port D pin is an input or an output. Writing a 1
to a DDRD bit enables the output buffer for the corresponding port D pin; a 0 disables the output buffer.
DDRD6–DDRD0 — Data Direction Register D Bits
Freescale Semiconductor
The PTD5/T1CH1–PTD4/T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level
select bits, ELSxB and ELSxA, determine whether the PTD5/T1CH1–PTD4/T1CH0 pins are timer
channel I/O pins or general-purpose I/O pins. See
TIM2).
The PTD3/SPSCK pin is the serial clock input of the SPI module. When the SPE bit is clear, the
PTD3/SPSCK pin is available for general-purpose I/O.
The PTD2/MOSI pin is the master out/slave in terminal of the SPI module. When the SPE bit is clear,
the PTD2/MOSI pin is available for general-purpose I/O.
The PTD1/MISO pin is the master in/slave out terminal of the SPI module. When the SPI enable bit,
SPE, is clear, the SPI module is disabled, and the PTD0/SS pin is available for general-purpose I/O.
Data direction register D (DDRD) does not affect the data direction of port D pins that are being used
by the SPI module. However, the DDRD bits always determine whether reading port D returns the
states of the latches or the states of the pins. See
The PTD0/SS pin is the slave select input of the SPI module. When the SPE bit is clear, or when the
SPI master bit, SPMSTR, is set, the PTD0/SS pin is available for general-purpose I/O. When the SPI
is enabled, the DDRB0 bit in data direction register B (DDRB) has no effect on the PTD0/SS pin.
These read/write bits control port D data direction. Reset clears DDRD6–DDRD0, configuring all port D
pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
Address:
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Reset:
Read:
Write:
$0007
Bit 7
0
0
Figure 12-14. Data Direction Register D (DDRD)
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
= Unimplemented
DDRD6
6
0
DDRD5
5
0
NOTE
DDRD4
4
0
Table
Chapter 17 Timer Interface Module (TIM1 and
DDRD3
12-5.
3
0
DDRD2
2
0
DDRD1
1
0
DDRD0
Bit 0
0
Port D
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