R5F21257SYFP#U0 Renesas Electronics America, R5F21257SYFP#U0 Datasheet - Page 141
![MCU 2KB FLASH 48K 52-LQFP](/photos/28/61/286101/52-lqfp_sml.jpg)
R5F21257SYFP#U0
Manufacturer Part Number
R5F21257SYFP#U0
Description
MCU 2KB FLASH 48K 52-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/25r
Specifications of R5F21257SYFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 105°C
Package / Case
52-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
12.5
Figure 12.19
Table 12.8
Timer RD
Clock synchronous serial
I/O with chip select
I
2
The timer RD (channel 0) interrupt, timer RD (channel 1) interrupt, clock synchronous serial I/O with chip select
interrupt, and I
generated by the logical OR of several interrupt request factors and is reflected in the IR bit in the corresponding
interrupt control register. Therefore, each of these peripheral functions has its own interrupt request source status
register (status register) and interrupt request source enable register (enable register) to control the generation of
interrupt requests (change the IR bit in the interrupt control register). Table 12.8 lists the Registers Associated with
Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupt, and I
Figure 12.19 shows a Block Diagram of Timer RD Interrupt.
C bus interface
Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select
Interrupts, and I
Request Sources)
Feb 29, 2008
Channel 0
Channel 1
Chip Select Interrupt, and I
Registers Associated with Timer RD Interrupt, Clock Synchronous Serial I/O with
Block Diagram of Timer RD Interrupt
2
i = 0 or 1
IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register
IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIER register
C bus interface interrupt each have multiple interrupt request sources. An interrupt request is
OVIE bit
UDF bit
OVF bit
Page 122 of 485
Channel i
TRDSR0
TRDSR1
SSSR
ICSR
Interrupt Request Source
2
IMIEA bit
IMIEB bit
IMIEC bit
IMIED bit
C bus Interface Interrupt (Interrupts with Multiple Interrupt
IMFC bit
IMFD bit
IMFA bit
IMFB bit
Status Register of
2
C bus Interface Interrupt
Interrupt Request Source
TRDIER0
TRDIER1
SSER
ICIER
Enable Register of
Timer RD (channel i)
interrupt request
(IR bit in TRDiIC register)
2
C bus Interface Interrupt and
TRD0IC
TRD1IC
SSUIC
IICIC
Interrupt Control
Register
12. Interrupts
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