R5F21257SYFP#U0 Renesas Electronics America, R5F21257SYFP#U0 Datasheet - Page 168
![MCU 2KB FLASH 48K 52-LQFP](/photos/28/61/286101/52-lqfp_sml.jpg)
R5F21257SYFP#U0
Manufacturer Part Number
R5F21257SYFP#U0
Description
MCU 2KB FLASH 48K 52-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/25r
Specifications of R5F21257SYFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 105°C
Package / Case
52-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
14.1.6
• Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the
• Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by
• In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by
• When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and
• The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.
• When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler
• The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1
• When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow
• When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three
Feb 29, 2008
count starts.
the MCU. Consequently, the timer value may be updated during the period when these two registers are
being read.
writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the
READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0
although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or
TUNDF bit which is not supposed to be set to 0 with the MOV instruction.
TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.
immediately after the count starts, then set the TEDGF bit to 0.
(count starts) while the count is stopped.
During this time, do not access registers associated with timer RA
starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count).
The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RA
NOTE:
three or more cycles of the count source clock for each write interval.
or more cycles of the prescaler underflow for each write interval.
Notes on Timer RA
1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.
Page 149 of 485
(1)
(1)
other than the TCSTF bit.
other than the TCSTF bit. Timer RA
14. Timers
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