R5F21257SYFP#U0 Renesas Electronics America, R5F21257SYFP#U0 Datasheet - Page 393
![MCU 2KB FLASH 48K 52-LQFP](/photos/28/61/286101/52-lqfp_sml.jpg)
R5F21257SYFP#U0
Manufacturer Part Number
R5F21257SYFP#U0
Description
MCU 2KB FLASH 48K 52-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/25r
Specifications of R5F21257SYFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 105°C
Package / Case
52-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 17.6
Timer RA Set the timer to start counting
Timer RA Read the count status flag
Hardware LIN Read the Synch Break detection flag
Timer RA Set the timer to stop counting
Timer RA Read the count status flag
UART0 Communication via UART0
UART0 Communication via UART0
Feb 29, 2008
TE bit in U0C1 register ← 1
U0TB register ← 0055h
U0TB register ← ID field
TSTART bit in TRACR register ← 1
TCSTF flag in TRACR register
TSTART bit in TRACR register ← 0
TCSTF flag in TRACR register
Example of Header Field Transmission Flowchart (2)
SBDCT flag in LINST register
SBDCT = 1 ?
TCSTF = 1 ?
TCSTF = 0 ?
YES
YES
YES
Page 374 of 485
A
NO
NO
NO
Timer RA generates Synch Break.
If registers TRAPRE and TRA for
timer RA do not need to be read or
the register settings do not need to be
changed after writing 1 to the
TSTART bit, the procedure for reading
TCSTF flag = 1 can be omitted.
Zero to one cycle of the timer RA
count source is required after timer
RA starts counting before the TCSTF
flag is set to 1.
The timer RA interrupt may be used
to terminate generation of Synch
Break.
One to two cycles of the CPU clock
are required after Synch Break
generation completes before the
SBDCT flag is set to 1.
After timer RA Synch Break is
generated, the timer should be made
to stop counting.
If registers TRAPRE and TRA for timer
RA do not need to be read or the
register settings do not need to be
changed after writing 0 to the TSTART
bit, the procedure for reading TCSTF
flag = 0 can be omitted.
Zero to one cycle of the timer RA count
source is required after timer RA stops
counting before the TCSTF flag is set
to 0.
Transmit the Synch Field.
Transmit the ID field.
17. Hardware LIN
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