R5F21257SYFP#U0 Renesas Electronics America, R5F21257SYFP#U0 Datasheet - Page 520
![MCU 2KB FLASH 48K 52-LQFP](/photos/28/61/286101/52-lqfp_sml.jpg)
R5F21257SYFP#U0
Manufacturer Part Number
R5F21257SYFP#U0
Description
MCU 2KB FLASH 48K 52-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/25r
Specifications of R5F21257SYFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 105°C
Package / Case
52-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Rev.
1.00
2.00
REVISION HISTORY
May 31, 2006
Nov 01, 2006
Date
all pages “PTLG0064JA-A (64F0G)” package added
Page
468
469
2, 3
123
127
140
198
215
220
252
262
291
296
10
18
36
61
62
66
67
78
80
81
82
90
91
93
98
1
9
22. Notes on On-Chip Debugger; (2) revised
12.6.3 “and Table 20.18 (VCC = 5V), ... TRAIO Input, INT1 Input.”
Appendix 1. Package Dimensions
Y version added
Factory programming product added
1. Overview; “... or a 64-pin molded-plastic FLGA.“ added
Table 1.1 Functions and Specifications for R8C/24 Group, Table 1.2
Functions and Specifications for R8C/25 Group;
Figure 1.4 PLQP0052JA-A Package Pin Assignments (Top View);
Figure 1.5 PTLG0064JA-A Package Pin Assignments added
Table 4.1 revised
Figure 6.5 NOTE6 revised
Table 7.17 revised
Table 7.19 revised
Table 7.33, Table 7.35 revised
Table 7.36 revised
Figure 10.5 NOTE2 added
Figure 10.8 NOTE6 revised
Figure 10.9 revised
10.2.2 “Adjust the FRA1 register so that .... 40 MHz or less.” added
Figure 10.11 revised
Figure 10.12 revised
Figure 10.13 revised
10.7.1 revised, 10.7.2 added
deleted
Figure 13.2; Watchdog Timer Control Register: After Reset “When read,
the content is undefined.” added
Table 14.4; TRAO pin function: Specification “or pulse output” added
Figure 14.49 NOTE2 added
Figure 14.65 Timer RD Output Control Register NOTE2 added
Figure 14.71 revised
Figure 14.100 NOTE2 added
14.3.12.7 “Do not use the TRDGRC0 register in complementary PWM
mode.” deleted
Table 15.1 NOTE2 revised
Table 15.4 NOTE1 revised
R8C/24 Group, R8C/25 Group Hardware Manual
“The latest package ... Renesas Technology website.” added
Package: “64-pin molded-plastic FLGA” added
NOTE3 revised
C - 16
Description
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