MCF51EM256CLK Freescale Semiconductor, MCF51EM256CLK Datasheet - Page 246

• Manufacturer Part Number: MCF51EM256CLK
• Description: IC MCU 32BIT 256KB FLASH 80LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLK

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x16b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Interrupt Controller (CF1_INTC)
The INTC_PL6P7 register specifies the highest-priority, maskable interrupt request that is defined as the
level six, priority seven request. The INTC_PL6P6 register specifies the second-highest-priority, maskable
interrupt request defined as the level six, priority six request. Reset clears both registers, disabling any
request re-mapping.
For an example of the use of these registers, see
10.3.3
The interrupt controller provides a combinatorial logic path to generate a special wakeup signal to exit
from the wait or stop modes. The INTC_WCR register defines wakeup condition for interrupt recognition
during wait and stop modes. This mode of operation works as follows:
10-10
REQN
Offset: CF1_INTC_BASE + 0x18 (INTC_PL6P7)
Field
Reset
7–6
5–0
1. Write to the INTC_WCR to enable this operation (set INTC_WCR[ENB]) and define the interrupt
2. Execute a stop instruction to place the processor into wait or stop mode.
3. After the processor is stopped, the interrupt controller enables special logic that evaluates the
4. If an active interrupt request is asserted and the resulting interrupt level is greater than the mask
W
R
mask level needed to force the core to exit wait or stop mode (INTC_WCR[MASK]). The
maximum value of INTC_WCR[MASK] is 0x6 (0b110). The INTC_WCR is enabled with a mask
level of 0 as the default after reset.
incoming interrupt sources in a purely combinatorial path; no clocked storage elements are
involved.
value contained in INTC_WCR[MASK], the interrupt controller asserts the wakeup output signal.
This signal is routed to the clock generation logic to exit the low-power mode and resume
processing.
CF1_INTC_BASE + 0x19 (INTC_PL6P6)
Reserved, must be cleared.
Request number. Defines the peripheral IRQ number to be remapped as the level 6, priority 7 (for INTC_PL6P7)
request and level 6, priority 6 (for INTC_PL6P6).
Note: The value must be in a valid interrupt number. Unused or reserved interrupt numbers are ignored.
INTC Wakeup Control Register (INTC_WCR)
0
0
7
Figure 10-3. Programmable Level 6, Priority {7,6} Registers (INTC_PL6P{7,6})
The requests associated with the INTC_FRC register have a fixed level and
priority that cannot be altered.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
0
0
6
Table 10-5. INTC_PL6P{7,6} Field Descriptions
0
5
Section 10.6.2, “Using INTC_PL6P{7,6} Registers.”
NOTE
0
4
Description
3
0
REQN
0
2
Freescale Semiconductor
0
1
Access: Read/Write
0
0