MCF51EM256CLK Freescale Semiconductor, MCF51EM256CLK Datasheet - Page 60

• Manufacturer Part Number: MCF51EM256CLK
• Description: IC MCU 32BIT 256KB FLASH 80LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLK

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x16b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Memory
The section of memory at 0x(00)C0_0000 is assigned for use by the ColdFire rapid GPIO module. See
Table 3-4
the module.
The MCF51EM256 series microcontrollers include 8-bit and 16-bit peripheral busses. The bus bridge from
the ColdFire system bus to the peripheral bus is capable of serializing 32-bit accesses into two 16-bit
accesses or four 8-bit accesses. This can be used to speed access to properly aligned peripheral registers.
Note, not all peripheral registers are aligned to take advantage of this feature.
CPU accesses to those parts of the memory map marked as not implemented in
address reset if CPUCR[ARD] = 0 or an address error exception if CPUCR[ARD] = 1.
The lower 32 KB of flash memory and slave peripherals section of the memory map are most efficiently
accessed using the ColdFire absolute short addressing mode. RAM is most efficiently accessed using the
A5-relative addressing mode (address register indirect with displacement mode).
3.2
The ColdFire interrupt controller module is mapped in the peripheral space and occupies a 64-byte space
at the upper end of memory. Accordingly, its address decode is defined as
0x(FF)FF_FFC0–0x(FF)FF_FFFF. This 64-byte space includes the program-visible interrupt controller
registers as well as the space used for interrupt acknowledge (IACK) cycles.
There is a nonvolatile register area consisting of a block of 20 bytes in flash memory as shown in
Table
Because the nonvolatile register locations are flash memory, they must be erased and programmed like
other flash memory locations. MCF51EM256 series have two sets of nonvolatile registers, one for each
flash block. Refer to
Table 3-3
associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a
3-4
•
•
LCD Module
3-15. Nonvolatile register locations include:
RESERVED
Peripheral
NVPROT and NVOPT are loaded into working registers at reset
An 8-byte backdoor comparison key that optionally allows a user to gain controlled access to
secure memory
FTSR
FTSR
INTC
PDB
Detailed Register Addresses and Bit Assignments
for the rapid GPIO memory map and
is a summary of all user-accessible peripheral registers and control bits. Cells that are not
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Section 3.6, “Flash Module Reserved Memory
Reserved Memory
Flash Wrapper
Flash Wrapper
Programmable Delay Block
V1 ColdFire Interrupt Controller
LCD Module
Table 3-2. High Level Peripheral Memory Map (continued)
Description
Chapter 5, “Rapid GPIO (RGPIO),”
Locations,” for detailed information.
Instance Name
FTSR1
FTSR2
NONE
INTC
LCD
PDB
Table 3-2
for further details on
Freescale Semiconductor
result in an illegal
0x(FF)FF_FFC0
0x(FF)FF_86A0
0x(FF)FF_87A0
0x(FF)FF_E000
0x(FF)FF_8700
0x(FF)FF_8780
Base Address