MCF51EM256CLK Freescale Semiconductor, MCF51EM256CLK Datasheet - Page 261

• Manufacturer Part Number: MCF51EM256CLK
• Description: IC MCU 32BIT 256KB FLASH 80LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLK

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x16b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.1.9.4
In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the internal reference clock. The BDC clock is not available.
11.1.9.5
In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is
bypassed. The ICS supplies a clock derived from the external reference clock source. The BDC clock is
supplied from the FLL.
11.1.9.6
In FLL bypassed external low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the external reference clock. The BDC clock is not available.
11.1.9.7
In stop mode, the FLL is disabled and the internal or the ICS external reference clocks source (OSCOUT)
can be selected to be enabled or disabled. The BDC clock is not available and the ICS does not provide an
MCU clock source.
11.2
There are no ICS signals that connect off chip.
11.3
Figure 11-6
Freescale Semiconductor
ICSTRM
ICSC1
ICSC2
Name
External Signal Description
Register Definition
is a summary of ICS registers.
FLL Bypassed Interna
FLL Bypassed Externa
FLL Bypassed Externa
Stop (STOP)
The DCO frequency changes from the pre-stop value to its reset value and
the FLL will need to re-acquire the lock before the frequency is stable.
Timing sensitive operations should wait for the FLL acquistition time,
tAquire, before executing.
W
W
W
R
R
R
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
7
CLKS
BDIV
6
Table 11-6. ICS Register Summary
RANGE
5
l Low Power (FBILP)
l (FBE)
l Low Power (FBELP)
NOTE
RDIV
HGO
4
TRIM
LP
3
EREFS
IREFS
2
ERCLKEN
IRCLKEN
Internal Clock Source (ICS)
1
EREFSTEN
IREFSTEN
0
11-7