DF36054GFPJ Renesas Electronics America, DF36054GFPJ Datasheet - Page 234
![MCU 3/5V 32K J-TEMP POR&LVD 64-Q](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36054GFPJ
Manufacturer Part Number
DF36054GFPJ
Description
MCU 3/5V 32K J-TEMP POR&LVD 64-Q
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36054GFPJ
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F36054GFPJ
HD64F36054GFPJ
HD64F36054GFPJ
- Current page: 234 of 594
- Download datasheet (4Mb)
Section 12 Timer Z
12.4.5
In PWM mode, PWM waveforms are output from the FTIOB, FTIOC, and FTIOD output pins
with GRA as a cycle register and GRB, GRC, and GRD as duty registers. The initial output level
of the corresponding pin depends on the setting values of TOCR and POCR. Table 12.3 shows an
example of the initial output level of the FTIOB0 pin.
The output level is determined by the POLB to POLD bits corresponding to POCR. When POLB
is 0, the FTIOB output pin is set to 0 by compare match B and set to 1 by compare match A. When
POLB is 1, the FTIOB output pin is set to 1 by compare match B and cleared to 0 by compare
match A. In PWM mode, maximum 6-phase PWM outputs are possible.
Figure 12.21 shows an example of the PWM mode setting procedure.
Table 12.3 Initial Output Level of FTIOB0 Pin
TOB0
0
0
1
1
Rev. 4.00 Mar. 15, 2006 Page 200 of 556
REJ09B0026-0400
PWM Mode
POLB
0
1
0
1
Initial Output Level
1
0
0
1
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