DF36054GFPJ Renesas Electronics America, DF36054GFPJ Datasheet - Page 401
![MCU 3/5V 32K J-TEMP POR&LVD 64-Q](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36054GFPJ
Manufacturer Part Number
DF36054GFPJ
Description
MCU 3/5V 32K J-TEMP POR&LVD 64-Q
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36054GFPJ
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F36054GFPJ
HD64F36054GFPJ
HD64F36054GFPJ
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[1]
[2]
[3]
[4]
[5]
[6]
[7]
No
No
Figure 16.8 Sample Serial Reception Flowchart (MSS = 1)
Dummy read on SSRDR
RE = 0, RSSTP = 0
Read receive data
Read receive data
Set RSSTP to 1
Last reception?
Read ORER
Read ORER
Read RDRF
Read RDRF
Initialization
ORER = 1?
ORER = 1?
RDRF = 1?
RDRF = 1?
in SSRDR
in SSRDR
Start
End
No
No
Yes
No
Yes
Yes
Yes
Yes
Overrun error
processing
Section 16 Synchronous Serial Communication Unit (SSU)
[1] After setting each register in the SSU,
[2] Determine whether the last one byte of
[3][6] When a receive error occurs, clear the
[4] Confirm that the RDRF bit is 1. If the RDRF
[5] Before the last one byte of data is received,
[7] Confirm that the RDRF bit is 1. To end
dummy read on SSRDR is performed
and reception is started.
data is received. When the last one byte
of data is received, set to stop reception
after the data is received.
bit is 1, receive data in SSRDR is read. If the
SSRDR bit is read, the RDRF bit is automatically
cleared.
set the RSSTP bit to 1 and reception is stopped
after the data is received.
reception, clear the RE and RSSTP bits to
0 and then read the last receive data. If the
SSRDR bit is read before clearing the RE bit,
reception is started again.
ORER flag to 0 after the ORER flag in
SSSR is read and an appropriate error
processing is performed. When the ORER
flag is set to 1, transmission/reception
cannot be started again.
Rev. 4.00 Mar. 15, 2006 Page 367 of 556
REJ09B0026-0400
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