DF36054GFPJ Renesas Electronics America, DF36054GFPJ Datasheet - Page 308
![MCU 3/5V 32K J-TEMP POR&LVD 64-Q](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36054GFPJ
Manufacturer Part Number
DF36054GFPJ
Description
MCU 3/5V 32K J-TEMP POR&LVD 64-Q
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36054GFPJ
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F36054GFPJ
HD64F36054GFPJ
HD64F36054GFPJ
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Section 14 Serial Communication Interface 3 (SCI3)
14.4.4
Figure 14.7 shows an example of operation for reception in asynchronous mode. In serial
reception, the SCI3 operates as described below.
1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs
2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive
5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
Rev. 4.00 Mar. 15, 2006 Page 274 of 556
REJ09B0026-0400
Serial
data
RDRF
FER
LSI
operation
User
processing
internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an
ERI interrupt request is generated. Receive data is not transferred to RDR.
RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated.
data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt
request is generated.
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated. Continuous reception is possible because the RXI interrupt routine reads the receive
data transferred to RDR before reception of the next receive data has been completed.
Serial Data Reception
1
Start
bit
Figure 14.7 Example of SCI3 Reception in Asynchronous Mode
0
D0
D1
Receive
1 frame
data
(8-Bit Data, Parity, One Stop Bit)
D7
Parity
0/1
bit
RXI request
Stop
bit
1
Start
bit
0
D0
RDRF
cleared to 0
RDR data read
1 frame
D1
Receive
data
D7
Parity
0/1
bit
Stop
bit
0
0 stop bit
detected
Mark state
(idle state)
1
ERI request in
response to
framing error
Framing error
processing
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