DF36054GFPJ Renesas Electronics America, DF36054GFPJ Datasheet - Page 430
![MCU 3/5V 32K J-TEMP POR&LVD 64-Q](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36054GFPJ
Manufacturer Part Number
DF36054GFPJ
Description
MCU 3/5V 32K J-TEMP POR&LVD 64-Q
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36054GFPJ
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F36054GFPJ
HD64F36054GFPJ
HD64F36054GFPJ
- Current page: 430 of 594
- Download datasheet (4Mb)
Section 18 A/D Converter
18.3.3
ADCR enables A/D conversion started by an external trigger signal.
Rev. 4.00 Mar. 15, 2006 Page 396 of 556
REJ09B0026-0400
Bit
2
1
0
Bit
7
6 to 1
0
Bit Name
CH2
CH1
CH0
Bit Name
TRGE
—
—
A/D Control Register (ADCR)
Initial
Value
0
0
0
Initial
Value
0
All 1
0
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
Description
Channel Select 2 to 0
Select analog input channels.
When SCAN = 0
000: AN0
001: AN1
010: AN2
011: AN3
100: AN4
101: AN5
110: AN6
111: AN7
Description
Trigger Enable
A/D conversion is started at the falling edge and the rising
edge of the external trigger signal (ADTRG) when this bit
is set to 1.
The selection between the falling edge and rising edge of
the external trigger pin (ADTRG) conforms to the WPEG5
bit in the interrupt edge select register 2 (IEGR2)
Reserved
These bits are always read as 1.
Reserved
Although this bit is readable/writable, do not set this bit to
1.
When SCAN = 1
000: AN0
001: AN0 and AN1
010: AN0 to AN2
011: AN0 to AN3
100: AN4
101: AN4 and AN5
110: AN4 to AN6
111: AN4 to AN7
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