DF36054GFPJ Renesas Electronics America, DF36054GFPJ Datasheet - Page 283
![MCU 3/5V 32K J-TEMP POR&LVD 64-Q](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36054GFPJ
Manufacturer Part Number
DF36054GFPJ
Description
MCU 3/5V 32K J-TEMP POR&LVD 64-Q
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36054GFPJ
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F36054GFPJ
HD64F36054GFPJ
HD64F36054GFPJ
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13.3
The watchdog timer is provided with an 8-bit counter. If 1 is written to WDON while writing 0 to
B2WI when the TCSRWE bit in TCSRWD is set to 1, TCWD begins counting up. (To operate the
watchdog timer, two write accesses to TCSRWD are required.) When a clock pulse is input after
the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset
signal is generated. The internal reset signal is output for a period of 256
is a writable counter, and when a value is set in TCWD, the count-up starts from that value. An
overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the
TCWD set value.
Figure 13.2 shows an example of watchdog timer operation.
Example:
Operation
Internal reset
signal
count value
TCWD
With 30-ms overflow period when
Therefore, 256 – 15 = 241 (H'F1) is set in TCW.
H'FF
H'00
4
8192
10
H'F1
Figure 13.2 Watchdog Timer Operation Example
6
H'F1 written
to TCWD
30
10
–3
Start
= 14.6
H'F1 written to TCWD
= 4 MHz
Rev. 4.00 Mar. 15, 2006 Page 249 of 556
256
Reset generated
osc
TCWD overflow
clock cycles
Section 13 Watchdog Timer
osc
clock cycles. TCWD
REJ09B0026-0400
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