COP8CCR9IMT8/NOPB National Semiconductor, COP8CCR9IMT8/NOPB Datasheet - Page 23

• Manufacturer Part Number: COP8CCR9IMT8/NOPB
• Description: IC MCU EEPROM 8BIT 32K 48-TSSOP
• Manufacturer: National Semiconductor
• Series: COP8™ 8Cr

Specifications of COP8CCR9IMT8/NOPB

• Core Processor: COP8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: Microwire/Plus (SPI), UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSSOP
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 1 KB
• On-chip Adc: 10 bit, 16 channel
• Number Of Programmable I/os: 59
• Number Of Timers: 3
• Height: 0.9 mm
• Interface Type: SPI, USART
• Length: 12.5 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 6.1 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: *COP8CCR9IMT8; *COP8CCR9IMT8/NOPB; COP8CCR9IMT8

10.0 Functional Description
The format of the Option register is as follows:
Bits 7, 6 These bits are reserved and must be 0.
Bit 5
Bits 4, 3 These bits are reserved and must be 0.
Bit 2
Bit 1
Bit 0
The COP8 assembler defines a special ROM section type,
CONF, into which the Option Register data may be coded.
The Option Register is programmed automatically by pro-
grammers that are certified by National.
The user needs to ensure that the FLEX bit will be set when
the device is programmed.
The following examples illustrate the declaration of the Op-
tion Register.
Syntax:
[label:].sect
Example: The following sets a value in the Option Register
and User Identification for a COP8CBR9HVA7. The Option
Register bit values shown select options: Security disabled,
WATCHDOG enabled HALT mode enabled and execution
will commence from Flash Memory.
Note: All programmers certified for programming this family
of parts will support programming of the Option Register.
Please contact National or your device programmer supplier
for more information.
(Continued)
Bit 7
= 1
= 0
= 1
= 0
= 1
= 0
= 1
= 0
.chip
.sect
.db
.endsect
...
.end
Reserved
Bit 6
Security enabled. Flash Memory read and write
are not allowed except in User ISP/Virtual E
mands. Mass Erase is allowed.
Security disabled. Flash Memory read and write
are allowed.
WATCHDOG feature disabled. G1 is a general
purpose I/O.
WATCHDOG
WATCHDOG output with weak pullup.
HALT mode disabled.
HALT mode enabled.
Execution following RESET will be from Flash
Memory.
Flash Memory is erased. Execution following RE-
SET will be from Boot ROM with the MICROWIRE/
PLUS ISP routines.
.db
.endsect
SECURITY
Bit 5
8CBR
option, conf
0x01
start
config, conf
value
Bit 4
feature
Reserved
Bit 3
;wd, halt, flex
enabled.
;1 byte,
;configures
;options
WATCH
Bit 2
DOG
HALT
Bit 1
G1
pin
2
FLEX
Bit 0
com-
is
23
10.6 SECURITY
The device has a security feature which, when enabled,
prevents external reading of the Flash program memory. The
security bit in the Option Register determines, whether se-
curity is enabled or disabled. If the security feature is dis-
abled, the contents of the internal Flash Memory may be
read by external programmers or by the built in
MICROWIRE/PLUS serial interface ISP. Security must be
enforced by the user when the contents of the Flash
Memory are accessed via the user ISP or Virtual EE-
PROM capability.
If the security feature is enabled, then any attempt to exter-
nally read the contents of the Flash Memory will result in the
value FF (hex) being read from all program locations (except
the Option Register). In addition, with the security feature
enabled, the write operation to the Flash program memory
and Option Register is inhibited. Page Erases are also inhib-
ited when the security feature is enabled. The Option Reg-
ister is readable regardless of the state of the security bit by
accessing location FFFF (hex). Mass Erase Operations are
possible regardless of the state of the security bit.
The security bit can be erased only by a Mass Erase of the
entire contents of the Flash unless Flash operation is under
the control of User ISP functions.
Note: The actual memory address of the Option Register is
7FFF (hex), however the MICROWIRE/PLUS ISP routines
require the address FFFF (hex) to be used to read the
Option Register when the Flash Memory is secured.
The entire Option Register must be programmed at one time
and cannot be rewritten without first erasing the entire last
page of Flash Memory.
10.7 RESET
The device is initialized when the RESET pin is pulled low or
the On-chip Brownout Reset is activated. The Brownout
Reset feature is not available on the COP8CDR9.
The following occurs upon initialization:
Port A: TRI-STATE (High Impedance Input)
Port B: TRI-STATE (High Impedance Input)
Port C: TRI-STATE (High Impedance Input)
Port D: HIGH
Port E: TRI-STATE (High Impedance Input)
Port F: TRI-STATE (High Impedance Input)
Port L: TRI-STATE (High Impedance Input)
PC: CLEARED to 0000
PSW, CNTRL and ICNTRL registers: CLEARED
SIOR:
Port G: TRI-STATE (High Impedance Input). Exceptions: If
Watchdog is enabled, then G1 is Watchdog output. G0
and G2 have their weak pull-up enabled during RESET.
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
FIGURE 8. Reset Logic
10137411
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