COP8CCR9IMT8/NOPB National Semiconductor, COP8CCR9IMT8/NOPB Datasheet - Page 80

• Manufacturer Part Number: COP8CCR9IMT8/NOPB
• Description: IC MCU EEPROM 8BIT 32K 48-TSSOP
• Manufacturer: National Semiconductor
• Series: COP8™ 8Cr

Specifications of COP8CCR9IMT8/NOPB

• Core Processor: COP8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: Microwire/Plus (SPI), UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSSOP
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 1 KB
• On-chip Adc: 10 bit, 16 channel
• Number Of Programmable I/os: 59
• Number Of Timers: 3
• Height: 0.9 mm
• Interface Type: SPI, USART
• Length: 12.5 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 6.1 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: *COP8CCR9IMT8; *COP8CCR9IMT8/NOPB; COP8CCR9IMT8

www.national.com
21.0 Development Support
The following companies have approved COP8 programmers in a variety of configurations. Contact your vendor’s local office
or distributor and request a COP8FLASH update. You can link to their web sites and get the latest listing of approved
programmers at: www.national.com/cop8.
Advantech; BP Microsystems; Data I/O; Dataman; Hi-Lo Systems; KANDA, Lloyd Research; MQP; Needhams; Phyton; SofTec
Microsystems; System General; and Tribal Microsystems.
22.0 Revision History
October 2000
April 2001
May 2001
Sept., 2001
January 2002
April 2002
August 2003
KANDA Systems
LTD.
K and K
Development ApS
National
Semiconductor
SofTec Microsystems Via Roma, 1
Date
Vendor
Throughout
Electrical Specifications
In-System Programming Clarified use of high voltage on G6 pin to force execution from Boot ROM.
Development Support
Forced Execution from
Boot ROM
Pin Descriptions
Timers
Development Support
Pin Descriptions
Reset
Power Saving Features
A/D Converter
Specifications
Development Support
Unit 17 -18
Glanyrafon Enterprise Park,
Aberystwyth, Ceredigion,
SY23 3JQ, UK
Tel: [phone]
Fax: [phone]
Kaergaardsvej 42 DK-8355
Solbjerg Denmark
Fax: [phone]
2900 Semiconductor Dr.
Santa Clara, CA 95051
USA
Tel: [phone]
Fax: [phone]
33082 Azzano Decimo (PN)
Italy
Tel: [phone]
Fax: [phone]
Section
Home Office
Base revision for this history.
Various typographical errors.
Reduced dynamic supply current specification.
Reduced input leakage current.
Added general statement regarding specification limits.
Added temp range 7 (−40˚C to +125˚C)
Added LLP and TSSOP Packages
Updated with the latest support information.
Added Figure.
Caution on GND connection on LLP package.
Clarification on high speed PWM Timer use.
Updated with the latest support information.
Clarification of the functions of L4 and L6 for T2 and T3 PWM Output.
Addition of caution regarding rising edge on RESET with low V
Description of modified function of ITMR Register.
Updated specifications to reflect final product and test specifications.
Updated with the latest support information.
Released as final.
(Continued)
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Summary of Changes
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