COP8CCR9IMT8/NOPB National Semiconductor, COP8CCR9IMT8/NOPB Datasheet - Page 3

• Manufacturer Part Number: COP8CCR9IMT8/NOPB
• Description: IC MCU EEPROM 8BIT 32K 48-TSSOP
• Manufacturer: National Semiconductor
• Series: COP8™ 8Cr

Specifications of COP8CCR9IMT8/NOPB

• Core Processor: COP8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: Microwire/Plus (SPI), UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSSOP
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 1 KB
• On-chip Adc: 10 bit, 16 channel
• Number Of Programmable I/os: 59
• Number Of Timers: 3
• Height: 0.9 mm
• Interface Type: SPI, USART
• Length: 12.5 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 6.1 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: *COP8CCR9IMT8; *COP8CCR9IMT8/NOPB; COP8CCR9IMT8

1.0 General Description ..................................................................................................................................... 1
2.0 Features ....................................................................................................................................................... 1
3.0 Block Diagram .............................................................................................................................................. 2
4.0 Ordering Information .................................................................................................................................... 2
5.0 Connection Diagrams ................................................................................................................................... 6
6.0 Architectural Overview ............................................................................................................................... 10
7.0 Absolute Maximum Ratings ....................................................................................................................... 12
8.0 Electrical Characteristics ............................................................................................................................ 12
9.0 Pin Descriptions ......................................................................................................................................... 18
10.0 Functional Description .............................................................................................................................. 20
11.0 In-System Programming ........................................................................................................................... 28
12.0 Timers ....................................................................................................................................................... 35
6.1 EMI REDUCTION .................................................................................................................................... 10
6.2 IN-SYSTEM PROGRAMMING AND VIRTUAL EEPROM ...................................................................... 10
6.3 DUAL CLOCK AND CLOCK DOUBLER ................................................................................................. 10
6.4 TRUE IN-SYSTEM EMULATION ............................................................................................................ 10
6.5 ARCHITECTURE
6.6 INSTRUCTION SET ............................................................................................................................... 10
6.7 PACKAGING/PIN EFFICIENCY .............................................................................................................. 11
9.1 EMULATION CONNECTION ................................................................................................................... 20
10.1 CPU REGISTERS ................................................................................................................................. 20
10.2 PROGRAM MEMORY ........................................................................................................................... 20
10.3 DATA MEMORY .................................................................................................................................... 20
10.4 DATA MEMORY SEGMENT RAM EXTENSION .................................................................................. 21
10.5 OPTION REGISTER ............................................................................................................................. 22
10.6 SECURITY ............................................................................................................................................ 23
10.7 RESET ................................................................................................................................................... 23
10.8 OSCILLATOR CIRCUITS ...................................................................................................................... 26
10.9 CONTROL REGISTERS ....................................................................................................................... 27
11.1 INTRODUCTION ................................................................................................................................... 28
11.2 FUNCTIONAL DESCRIPTION .............................................................................................................. 28
11.3 REGISTERS .......................................................................................................................................... 29
11.4 MANEUVERING BACK AND FORTH BETWEEN FLASH MEMORY AND BOOT ROM ..................... 30
11.5 FORCED EXECUTION FROM BOOT ROM ......................................................................................... 30
11.6 RETURN TO FLASH MEMORY WITHOUT HARDWARE RESET ....................................................... 31
11.7 MICROWIRE/PLUS ISP ........................................................................................................................ 31
11.8 USER ISP AND VIRTUAL E
11.9 RESTRICTIONS ON SOFTWARE WHEN CALLING ISP ROUTINES IN BOOT ROM ....................... 34
11.10 FLASH MEMORY DURABILITY CONSIDERATIONS ........................................................................ 34
6.6.1 Key Instruction Set Features ............................................................................................................. 10
6.6.2 Single Byte/Single Cycle Code Execution
6.6.3 Many Single-Byte, Multi-Function Instructions .................................................................................. 10
6.6.4 Bit-Level Control ................................................................................................................................ 11
6.6.5 Register Set ....................................................................................................................................... 11
10.4.1 Virtual EEPROM .............................................................................................................................. 22
10.7.1 External Reset ................................................................................................................................. 24
10.7.2 On-Chip Brownout Reset ................................................................................................................. 24
10.8.1 Oscillator .......................................................................................................................................... 26
10.8.2 Clock Doubler .................................................................................................................................. 27
10.9.1 CNTRL Register (Address X'00EE) ................................................................................................. 27
10.9.2 PSW Register (Address X'00EF) ..................................................................................................... 27
10.9.3 ICNTRL Register (Address X'00E8) ................................................................................................ 27
10.9.4 T2CNTRL Register (Address X'00C6) ............................................................................................. 27
10.9.5 T3CNTRL Register (Address X'00B6) ............................................................................................. 27
10.9.6 HSTCR Register (Address X'00AF) ................................................................................................ 28
10.9.7 ITMR Register (Address X'00CF) .................................................................................................... 28
10.9.8 ENAD Register (Address X'00CB) .................................................................................................. 28
11.3.1 ISP Address Registers ..................................................................................................................... 29
11.3.2 ISP Read Data Register .................................................................................................................. 29
11.3.3 ISP Write Data Register ................................................................................................................... 29
11.3.4 ISP Write Timing Register ................................................................................................................ 29
................................................................................................................................................................... 0
................................................................................................................................... 10
2
................................................................................................................ 32
Table of Contents
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