R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 1279
R5F61668MZN50FPV
Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668MZN50FPV.pdf
(1416 pages)
Specifications of R5F61668MZN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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The register list gives information on the on-chip I/O register addresses, how the register bits are
configured, and the register states in each operating mode. The information is given as shown
below.
1. Register addresses (address order)
• Registers are listed from the lower allocation addresses.
• Registers are classified according to functional modules.
• The number of Access Cycles indicates the number of states based on the specified reference
• Among the internal I/O register area, addresses not listed in the list of registers are undefined
2. Register bits
• Bit configurations of the registers are listed in the same order as the register addresses.
• Reserved bits are indicated by ⎯ in the bit name column.
• Space in the bit name field indicates that the entire register is allocated to either the counter or
• For the registers of 16 or 32 bits, the MSB is listed first.
• Byte configuration description order is subject to big endian.
3. Register states in each operating mode
• Register states are listed in the same order as the register addresses.
• For the initialized state of each bit, refer to the register description in the corresponding
• The register states shown here are for the basic operating modes. If there is a specific reset for
clock. For details, refer to section 9.5.4, External Bus Interface.
or reserved addresses. Undefined and reserved addresses cannot be accessed. Do not access
these addresses; otherwise, the operation when accessing these bits and subsequent operations
cannot be guaranteed.
data.
section.
an on-chip peripheral module, refer to the section on that on-chip peripheral module.
Section 29 List of Registers
Rev. 1.00 Jan. 29, 2010 Page 1247 of 1380
Section 29 List of Registers
REJ09B0596-0100
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