R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 526

• Manufacturer Part Number: R5F61668MZN50FPV
• Description: MCU FLASH 1024K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668MZN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 EXDMA Controller (EXDMAC)
11.5.9
An example of the basic bus cycle timing is shown in figure 11.23. In this example, word-size
transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus
mastership is transferred from the CPU to the EXDMAC, a source address read and destination
address write are performed. The bus is not released in response to another bus request, etc.,
between these read and write operations. As like CPU cycles, EXDMAC cycles conform to the
bus controller settings.
Rev. 1.00 Jan. 29, 2010 Page 494 of 1380
REJ09B0596-0100
Bφ
Address bus
RD
LLWR
LHWR
Bφ
Address bus
EXDMAC
control
Channel 0
Channel 1
Basic Bus Cycles
High
CPU cycle
Figure 11.23 Example of EXDMA Transfer Bus Timing
Figure 11.22 Example of Channel Priority Timing
Idle
Source address
T
1
Request
held
Request cleared
T
Channel 0
2
Selected
T
1
EXDMAC cycle (one word transfer)
Request cleared
Channel 0 transfer
T
2
Channel 0
Destination address
Channel 1
T
3
T
1
Channel 1 transfer
T
2
Channel 1
T
Idle
3
CPU cycle