R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 13

MCU FLASH 1024K ROM 144-LQFP

R5F61668MZN50FPV

Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61668MZN50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61668MZN50FPV
Manufacturer:
REA
Quantity:
5
Part Number:
R5F61668MZN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
8.4
8.5
Section 9 Bus Controller (BSC).........................................................................173
9.1
9.2
9.3
9.4
9.5
9.6
8.3.2
8.3.3
Operation .......................................................................................................................... 168
8.4.1
8.4.2
8.4.3
Usage Notes ...................................................................................................................... 170
Features............................................................................................................................. 173
Register Descriptions........................................................................................................ 176
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
9.2.10
9.2.11
9.2.12
9.2.13
9.2.14
9.2.15
9.2.16
9.2.17
9.2.18
Bus Configuration............................................................................................................. 210
Multi-Clock Function and Number of Access Cycles ...................................................... 211
External Bus...................................................................................................................... 215
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.5.6
Basic Bus Interface ........................................................................................................... 234
9.6.1
Break Address Mask Register n (BAMRA, BAMRB, BAMRC, BAMRD) .... 165
Break Control Register n (BRCRA, BRCRB, BRCRC, BRCRD) ................... 166
Setting of Break Control Conditions................................................................. 168
PC Break........................................................................................................... 168
Condition Match Flag ....................................................................................... 169
Bus Width Control Register (ABWCR)............................................................ 177
Access State Control Register (ASTCR) .......................................................... 178
Wait Control Registers A and B (WTCRA, WTCRB) ..................................... 179
Read Strobe Timing Control Register (RDNCR) ............................................. 184
CS Assertion Period Control Registers (CSACR) ............................................ 185
Idle Control Register (IDLCR) ......................................................................... 188
Bus Control Register 1 (BCR1) ........................................................................ 190
Bus Control Register 2 (BCR2) ........................................................................ 192
Endian Control Register (ENDIANCR)............................................................ 193
SRAM Mode Control Register (SRAMCR) ..................................................... 194
Burst ROM Interface Control Register (BROMCR)......................................... 195
Address/Data Multiplexed I/O Control Register (MPXCR) ............................. 197
DRAM Control Register (DRAMCR) .............................................................. 198
DRAM Access Control Register (DRACCR)................................................... 203
Synchronous DRAM Control Register (SDCR) ............................................... 204
Refresh Control Register (REFCR) .................................................................. 205
Refresh Timer Counter (RTCNT)..................................................................... 209
Refresh Time Constant Register (RTCOR) ...................................................... 209
Input/Output Pins.............................................................................................. 215
Area Division.................................................................................................... 219
Chip Select Signals ........................................................................................... 220
External Bus Interface....................................................................................... 221
Area and External Bus Interface ....................................................................... 226
Endian and Data Alignment.............................................................................. 231
Data Bus............................................................................................................ 234
Rev. 1.00 Jan. 29, 2010 Page xiii of xxxii

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