R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 17

• Manufacturer Part Number: R5F61668MZN50FPV
• Description: MCU FLASH 1024K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668MZN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.4
11.5
11.6
11.7
11.8
11.9
11.10 Usage Notes ...................................................................................................................... 545
Section 12 Data Transfer Controller (DTC) ......................................................547
12.1
12.2
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.3.7
11.3.8
Transfer Modes ................................................................................................................. 469
11.4.1
11.4.2
Mode Operation ................................................................................................................ 471
11.5.1
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
11.5.7
11.5.8
11.5.9
11.5.10 Bus Cycles in Dual Address Mode ................................................................... 495
11.5.11 Bus Cycles in Single Address Mode................................................................. 504
11.5.12 Operation Timing in Each Mode ...................................................................... 509
Operation in Cluster Transfer Mode ................................................................................. 520
11.6.1
11.6.2
11.6.3
11.6.4
11.6.5
Ending EXDMA Transfer................................................................................................. 537
Relationship among EXDMAC and Other Bus Masters................................................... 540
11.8.1
11.8.2
Interrupt Sources............................................................................................................... 542
Features............................................................................................................................. 547
Register Descriptions........................................................................................................ 549
12.2.1
EXDMA Destination Address Register (EDDAR)........................................... 449
EXDMA Offset Register (EDOFR).................................................................. 450
EXDMA Transfer Count Register (EDTCR).................................................... 451
EXDMA Block Size Register (EDBSR)........................................................... 452
EXDMA Mode Control Register (EDMDR) .................................................... 453
EXDMA Address Control Register (EDACR) ................................................. 462
Cluster Buffer Registers 0 to 7 (CLSBR0 to CLSBR7).................................... 468
Ordinary Modes ................................................................................................ 469
Cluster Transfer Modes..................................................................................... 470
Address Modes ................................................................................................. 471
Transfer Modes ................................................................................................. 474
Activation Sources............................................................................................ 479
Bus Mode.......................................................................................................... 480
Extended Repeat Area Function ....................................................................... 481
Address Update Function Using Offset ............................................................ 484
Registers during EXDMA Transfer Operation ................................................. 488
Channel Priority Order...................................................................................... 493
Basic Bus Cycles .............................................................................................. 494
Address Mode ................................................................................................... 520
Setting of Address Update Mode ...................................................................... 525
Caution for Combining with Extended Repeat Area Function ......................... 526
Bus Cycles in Cluster Transfer Dual Address Mode ........................................ 526
Operation Timing in Cluster Transfer Mode .................................................... 529
CPU Priority Control Function Over EXDMAC .............................................. 540
Bus Arbitration with Another Bus Master ........................................................ 541
DTC Mode Register A (MRA) ......................................................................... 550
Rev. 1.00 Jan. 29, 2010 Page xvii of xxxii