DF2317VTE25 Renesas Electronics America, DF2317VTE25 Datasheet - Page 496
DF2317VTE25
Manufacturer Part Number
DF2317VTE25
Description
MCU 3V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.D12312SVTE25V.pdf
(1146 pages)
Specifications of DF2317VTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
79
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2317VTE25
HD64F2317VTE25
HD64F2317VTE25
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Section 12 Serial Communication Interface (SCI)
12.3.2
In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the
start of communication and one or two stop bits indicating the end of communication. Serial
communication is thus carried out with synchronization established on a character-by-character
basis.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex
communication. Both the transmitter and the receiver also have a double-buffered structure, so
that data can be read or written during transmission or reception, enabling continuous data
transfer.
Figure 12.2 shows the general format for asynchronous serial communication.
In asynchronous serial communication, the communication line is usually held in the mark state
(high level). The SCI monitors the communication line, and when it goes to the space state (low
level), recognizes a start bit and starts serial communication.
One serial communication character consists of a start bit (low level), followed by data (in LSB-
first order), a parity bit (high or low level), and finally one or two stop bits (high level).
In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in
reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the
length of one bit, so that the transfer data is latched at the center of each bit.
Rev.7.00 Feb. 14, 2007 page 462 of 1108
REJ09B0089-0700
Serial
data
1
Operation in Asynchronous Mode
Start
bit
1 bit
0
LSB
Figure 12.2 Data Format in Asynchronous Communication
D0
One unit of transfer data (character or frame)
(Example with 8-Bit Data, Parity, Two Stop Bits)
D1
D2
Transmit/receive data
D3
7 or 8 bits
D4
D5
D6
MSB
D7
Parity
bit
1 bit,
or none
0/1
Stop bit(s)
1
1 or
2 bits
1
Idle state
(mark state)
1
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