DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 187
![MCU 3V 256K PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3026X25V
Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3026X25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 187 of 843
- Download datasheet (5Mb)
6.6.1
CPU: The CPU is the lowest-priority bus master. If an external bus master requests the bus while
the CPU has the bus right, the bus arbiter transfers the bus right to the bus master that requested it.
The bus right is transferred at the following times:
External Bus Master: When the BRLE bit is set to 1 in BRCR, the bus can be released to an
external bus master. The external bus master has highest priority, and requests the bus right from
the bus arbiter driving the
keeps the bus until the
master, the H8/3024 Group chip holds the address bus, data bus, bus control signals (
H W R
the
The bus arbiter samples the
is released to the external bus master at the appropriate opportunity. The
held low until the
When the
bus-release cycle.
Figure 6.20 shows the timing when the bus right is requested by an external bus master during a
read cycle in a two-state access area. There is a minimum interval of three states from when the
B R E Q
The bus right is transferred at the boundary of a bus cycle. If word data is accessed by two
consecutive byte accesses, however, the bus right is not transferred between the two byte
accesses.
If another bus master requests the bus while the CPU is performing internal operations, such as
executing a multiply or divide instruction, the bus right is transferred immediately. The CPU
continues its internal operations.
If another bus master requests the bus while the CPU is in sleep mode, the bus right is
transferred immediately.
B A C K
, and
signal goes low until the bus is released.
Operation
B R E Q
L W R
pin in the low output state.
) , and chip select signals (
pin is high in two consecutive samples, the
B A C K
B R E Q
signal goes low.
B R E Q
B R E Q
signal goes high. While the bus is released to an external bus
signal low. Once the external bus master acquires the bus, it
pin at the rise of the system clock ( ). If
C S
n : n = 7 to 0) in the high-impedance state, and holds
Rev. 2.00 Sep 20, 2005 page 147 of 800
B A C K
pin is driven high to end the
Section 6 Bus Controller
B R E Q
B R E Q
REJ09B0260-0200
signal should be
is low, the bus
A S
,
R D
,
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