DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 580
![MCU 3V 256K PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3026X25V
Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3026X25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 580 of 843
- Download datasheet (5Mb)
Section 18 Flash Memory [H8/3024F-ZTAT Version]
Bit 3—RAM Select (RAMS): Used with bits 2 to 1 to reassign an area to RAM (see table 18.5).
The initial setting for this bit is 0 in modes 5, 6, and 7 (internal flash memory enabled) and
programming is enabled. * In modes other than 5 to 7, 0 is always read and writing is disabled.
This bit is initialized by a reset and in hardware standby mode. It is not initialized in software
standby mode.
When 1 is written to the RAMS bit, all flash memory blocks are protected from programming and
erasing.
Bits 2 and 1—RAM2 and RAM1: These bits are used with bit 3 to reassign an area to RAM (see
table 18.5). The initial setting for this bit is 0 in modes 5, 6, and 7 (internal flash memory enabled)
and programming is enabled. * In modes other than 5 to 7, 0 is always read and writing is disabled.
These bits are initialized by a reset and in hardware standby mode. They are not initialized in
software standby mode.
Bit 0—Reserved: This bit cannot be modified and is always read as 1.
Note: * Flash memory emulation by RAM is not supported for mode 6 (single chip normal mode),
Table 18.5 RAM Area Setting
RAM Area
H'FFF000–H'FFF3FF
H'000000–H'0003FF
H'000400–H'0007FF
H'000800–H'000BFF
H'000C00–H'000FFF
Rev. 2.00 Sep 20, 2005 page 540 of 800
REJ09B0260-0200
so programming is possible, but do not set 1.
When performing flash memory emulation by RAM, the RAME bit in SYSCR must be set
to 1.
Bit 3
RAMS
0
1
1
1
1
Bit 2
RAM2
0/1
0
0
1
1
Bit 1
RAM1
0/1
0
1
0
1
RAM Emulation Status
No emulation
Mapping RAM
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