DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 29
DF3026X25V
Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3026X25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Figure 9.12
Figure 9.13
Figure 9.14
Figure 9.15
Figure 9.16
Figure 9.17
Figure 9.18
Figure 9.19
Figure 9.20
Figure 9.21
Figure 9.22
Figure 9.23
Figure 9.24
Section 10 Programmable Timing Pattern Controller (TPC)
Figure 10.1
Figure 10.2
Figure 10.3
Figure 10.4
Figure 10.5
Figure 10.6
Figure 10.7
Figure 10.8
Figure 10.9
Figure 10.10 Non-Overlapping Operation and NDR Write Timing ......................................... 336
Section 11 Watchdog Timer
Figure 11.1
Figure 11.2
Figure 11.3
Figure 11.4
Figure 11.5
Figure 11.6
Figure 11.7
Figure 11.8
Section 12 Serial Communication Interface
Figure 12.1
Figure 12.2
CMFB Flag Setting Timing when Input Capture Occurs .................................... 293
Timing of OVF Setting ........................................................................................ 293
TPC Block Diagram ............................................................................................ 312
TPC Output Operation......................................................................................... 328
Timing of Transfer of Next Data Register Contents and Output (Example) ....... 329
TPC Output Triggering by Input Capture (Example) .......................................... 334
Non-Overlapping TPC Output............................................................................. 335
Timing of Setting of OVF.................................................................................... 347
Timing of Setting of WRST Bit and Internal Reset............................................. 348
SCI Block Diagram.............................................................................................. 353
Timing of Clear by Input Capture........................................................................ 291
Timing of Input Capture Input Signal.................................................................. 292
CMF Flag Setting Timing when Compare Match Occurs ................................... 292
Example of Pulse Output ..................................................................................... 299
Contention between 8TCNT Write and Clear...................................................... 300
Contention between 8TCNT Write and Increment .............................................. 301
Contention between TCOR Write and Compare Match ...................................... 302
Contention between TCOR Read and Input Capture........................................... 303
Contention between Counter Clearing by Input Capture and Counter Increment 304
Contention between TCOR Write and Input Capture .......................................... 305
Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode . 306
Setup Procedure for Normal TPC Output (Example) .......................................... 330
Normal TPC Output Example (Five-Phase Pulse Output)................................... 331
Setup Procedure for Non-Overlapping TPC Output (Example) .......................... 332
Non-Overlapping TPC Output Example
(Four-Phase Complementary Non-Overlapping Pulse Output) ........................... 333
WDT Block Diagram........................................................................................... 338
Format of Data Written to TCNT and TCSR....................................................... 344
Format of Data Written to RSTCSR.................................................................... 345
Operation in Watchdog Timer Mode................................................................... 346
Interval Timer Operation ..................................................................................... 347
Contention between TCNT Write and Count up ................................................. 349
Data Format in Asynchronous Communication
(Example: 8-Bit Data with Parity and 2 Stop Bits).............................................. 383
Rev. 2.00 Sep 20, 2005 page xxvii of xxxviii
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